safe logic

Hello,

I am looking for designs for inherent failsafe logic gates using transistors and relais, i.e. gates that fail safely if any component fails.

An example for an AND would be two cascaded common emitter stages, the inputs applied to the collectors while the base of the first transistor is excited with a square wave. If any of the transistors fails the output will not be AC and therefore blocked by the transformer.

Input A Input B

| | .-. .-. | | | | | | | | '-' '-' | ------------. ,-->|- Output | | )|( |------- | )|( A AND B | | | -' '- | | | | | ___ |/ | |/ === === -|___|----| \\---| GND GND |> |>

square | | clock | | === === GND GND (created by AACircuit v1.28.6 beta 04/19/05

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Any article/book recommendations on this topic?

Many thanks!

Daniel

Anything in the railroad industry with the phrase "vital relay" will be of interest to you.

Most of the literature in that particular subfield is more than 20 or

30 years old.

There are a couple of commercial adaptations to non-relay implementations in the past couple of decades that are somewhat documented by their manufacturers/patent owners. Look for phrases like "vital interlocking processor", "vital processor for interlocking", "Mircolok II", etc. Many of these adaptations involve good old physical vital relays on the outputs but replace many of the intermediate layers with microprocessors and very clever (often proprietary, although I think some patents are expring by now) algorithms.

Tim.