There are a multitude of sources for information about FET gate-charge waveforms and drain switching analysis. But not so many about the effects of wiring inductance, etc.
Actually, it's a resonant ringing, and is most likely to happen at shutoff, at the end of your coil-current pulse. It's possible it could fail on the very first relay pulse. As for whether it's a positive or negative voltage that does the job, can't say. But I'll wager that PCB wiring inductance is involved.
That rules out ESD damage, I'd say.
I see you're giving up on the relay. But I hope you add some resistance and do enough testing to see if it helps. If you replace a bad mosfet, and run it for a while, is there a very high chance of failure again? High enough to be able to get an idea if it's working.
I use a pull down when driving FET's directly off a PIC as well. Most uC's on start-up default to input so a pull down ensures the FET stays off. I usually use 220k Bleeder gate to source or higher though.
Its a pretty low threshold FET are you sure your Vgs is going low enough to completely turn it off especially with a 10k pull down?
I don't know what uC your using but the worst case LOW on an I/O for a PIC can be as high as 0.6V At as little as 1.2mA. I've never seen it that high but it is the worst case.
You would figure a rupture of the gate oxide from over voltage would cause it to fail open. I've never had a FET fail that way usually when I blow one its pretty spectacular and obvious. ;-)
You really want to keep the loop for the gate source signal small as well as the drain source loop to reduce trace inductance. You should be using a gate resistor 4.7 to 22 ohm or a fusible resistor may be better in this case;-)
Oh and just because your not seeing ringing doesnt mean it isnt, you may just need a higher BW scope to see it. The gate oxide of such a low threshold fet wouldnt be to tolerant to overvoltage transients.
I did not give up, the decision was just made by my seniors to close the case by removing the whole circuit and feature in the unit cuz we we need to meet the project dead line.
Mean while, from experiments I just found out the even if the FET Gate and Drain is shorted, it does not really kill the MCU DIO pin at 5V. As the relay has 86 ohms, and DIO internal circuit has a regulation scheme which controls sinking current not to exceed 15mA, the DIO was not killed immediate if 5V is fed to it through 85 ohms at LOW condition. This leads to a series of tests on MCU, this is the really why I could not focus on FET yet.
But a decision also has been made to add relevant resistance between MCU and FET Gate in next design release.
With all the detailed discussion we've been having on ringing, spikes, and transient situations causing your failures, I'd have hoped by now that you would see that you can't always rely on simple steady-state stress analysis. Consider what extreme event is causing the mosfet to fail, and the processor's pin connected directly to the mosfet gate and this event. It's reasonable that it could take out the processor pin as well. I wouldn't waste any time testing the processor's robustness. I'd fix the design issue causing the fault event.