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rf traces

I am WAY too lazy to look at the board. Here are some thoughts. The most orthodox way to deal with the trace widths is to choose a stackup and trace width so that you get the desired impedance (50 Ohms). For surface layer traces, the only thing that really matters is the distance to the ground (or power) plane and the trace width. The copper thickness has a small effect also. It is certainly possible to create a stackup such that a 10 mil trace has a 50 Ohm impedance. I have done this. You end up using a fairly small gap between signal and plane, and a fairly large gap between plane and plane, assuming that the board is 62 mils overall.

If Maxim didn't use 50-Ohm traces, there could be a few possible explanations. It could be because they don't know any better or don't care, or they could have something up their sleeve. I have to assume that they know what they are doing, so I'll rule out the notion that they don't know any better.

They might not care about the impedance if the traces are very short. Afterall, if a trace is only 0.05 lambdas, then it doesn't really matter if the impedance is right.

Another possibility is that they use traces which are a little bit too narrow (high impedance) to compensate for the parasitic capacitance of the pads. I don't know if this really works, but I have heard people advocate it before. If you are really interested, you can go find the formulas for pad capacitance, and model the traces as lossless transmission lines and simulate it using spice or something similar. You could do 16 simulations for 4 different capacitances, and 4 different trace impedances. It might be just as easy to calculate the input impedance using a spreadsheet, since you are only using one frequency.

T1 _______________

---+--------) )-----+-----+ = C1 --------------- = C1 | | | \ GND GND / R1 \ / | GND

This is the setup when power is coming in from a connector to a device on the board. C1 is the capacitance of the connector pad, C2 is the capacitance of the receiving device pad, and R1 is meant to model the input impedance of the receiving device. If you have reason to believe that the input impedance is not 50 Ohms resistive (for example if you have a spice model or listed package parameters), then replace R1 with a more accurate impedance, Z1. T1 is the trace modelled as a transmission line.

If you are transmitting off board, then you could just sort of turn it around.

Have fun.

--Mac

Reply to
Mac
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looks like you need a W/h of about 2, so a *very* thin gap - IOW, 5 mils or so.

app notes are often written by the least skilled (usually the most junior) "engineers"

years ago, I tried some IR 1200V 1/2-bridge gatedrivers. We destroyed about 6 of them (2 demo boards) before giving up in disgust. 2 years later some IR bigwigs came to see why we weren't buying them. When told the sorry tale, they apologised profusely, and pointed out the pcb layout was so bad that pretty much *all* of the demo boards blew up. Didnt convince us to buy any though - too damn expensive.

probably the case. especially since its a demo board, so doesnt have to pass any sort of EMI tests.

slicing the pcb and measuring the top-to-mi1-layer spacing would be a good start.

Cheers Terry

Reply to
Terry Given

Hi,

In this eval board datasheet for the max2240 2.4GHz power amp:

"

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It shows the 50ohm RF input with a narrow (~10mil) trace, and also the RF output is conducted through a very narrow trace. Could someone explain why these narrow traces are used?

cheers, Jamie

Reply to
Jamie Morken

If there is GND on the same layer, how far away is it ? The closer, the lower the impedance of the narrow trace.

Rene

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Reply to
Rene Tschaggelar

Have a look at the circuit diagram on page 3. It gives the two track widths used (3.2mil and 5 mil), their lengths and electrical properties - to the left of C8

Geo

Reply to
Geo

maybe its used as a 1/4 wavelength matching line ?

Colin =^.^=

Reply to
colin

They are transmission lines: it is for the input and output matching. The data sheet will give more details.

Ken

Reply to
Ken Taylor

really? its a 4-layer pcb, assume 1.6mm thickness. if 0.4mm between top layer and 0V plane, then

t/h = 35um/0.4mm = 0.088 w/h = 0.254mm/0.8mm = 0.636

M.A.R. Gunston gives Zo = 87 ohms (or thereabouts) for FR4.

this suggests that:

1) I have no idea exactly how wide that trace is, 2) nor do I know what the top-to-0V separation distance is

but suggests the track *should* be wider than 10mils. thinner (or thicker) Cu has bugger all effect.

for 50 Ohms, 0.4mm spacing and 35um Cu, want W/h = 2 so 0.8mm wide traces = 31mils or so.

zooming in, I see 1" = 170mm, trace = 2mm wide, so 2/170 = 11.8mils, IOW Jamie wasnt far off. Perhaps the layer stackup is such that there is a VERY small gap between the trace and 0V? more likely the PCB layout is just wrong.

Cheers Terry

Reply to
Terry Given

no ground on the top layer. The PDF Jamie pointed to has all the artwork.

Reply to
Terry Given

They want to present some specific impedance to the PA. That is, they transform a nominal 50 Ohms on the output port to something else. You can likely come close to computing what it *theoretically* should be with the data they give.

However, there are some questionable areas when it comes to actual physical builds.

  1. They don't tell you if mask covers the traces, which does affect the line Z.
  2. They don't tell you the plating thickness. That 0.5 oz copper might be up to around 1.5 mil thick by the time they are done with copper and [other] plating.
  3. There is probably around a ±1 mil etching tolerance (width) when the fab is made. What this means is that for 5 mil and 3.6 mil (!) traces, there is a high fractional tolerance in line impedance.

I think the design is a bit dubious for production units, so for eval with it is also questionable if you're using the info to guess what might happen in production.

I wonder how close this chip is to the max2242 I used a few years back.

Reply to
keynes' old slave

10 mil wide microstrip on 6 mil FR-4 is just about 50 ohms.

John

Reply to
John Larkin

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