If a dim customer doesn't connect the sense pins, the feedback still happens, with a 50 ohm in the supply side, from sense(+) to V+ etc. It also works if sense wire breaks.
And, if the 50 ohm is in series with sense(+) between the sense wire and the feedback node, it keeps high power currents out of the skinny sense wire if the power wire breaks.
The first scenario is implied in some application literature. The second, I saw in my car some years back...
In my experience, any microcontroller attached to or running on externally accessible sense line juice will more likely fail on standard single-fault abnormals. They don't like pins being pulled above or below their own supply rails, or vice versa.
ie will need replacing/reprogramming, vs just recycle the source power, external or timed reset.
RL
Hi John, it's not clear the setup to me, could you draw the configuration please? I'll be more than happy to have a look for you.
KR Francesco.
And you think FPGA pins are more robust?
Something like this:
This remote sense scheme should allow for miswiring without blowing up the resistors, because we will shut down fast if a remote sense voltage gets too far from the corresponding output. Even if the resistor frying thing were fixed some other way, the shutdown is still valuable.
The two ADCs are isolated delta-sigmas. They are expensive and need an isolated power supply, so I only want two and want to have them share power.
Paralleling supplies will get interesting.
I should move the discharge circuit to the left of the current shunt so we don't measure it. Depletion fets or something.
Suggestions welcome.
Our policy is to never have semiconductor pins exposed to the outside world without protections.
Some ICs will clamp limited currents to their own rails with their ESD diodes, some won't.
Ahh. That looks suspiciously like assembly code. The horror!
There are lots of customers with air-gapped systems. The point of the query is to force the sales droid to tell you how to get that option, or admit (through clenched teeth) that they do not support that option.
Hmm. War story: Twenty years ago, I worked with a small company whose chief designer had been a cryptographer at NSA.
The FPGA design program (don't recall which one) did not allow one to fix the identity and location of the I/O pins, so every FPGA program spin randomly scrambled the pins, which raised havoc with the PC board layout, and so on. The FPGA design program had closed file formats, so the designer could not manually force things.
So the designer's inner cryptographer came out - he cracked the file format, if I recall using differential cryptanalysis methods, and then he could manually edit the files to maintain pin locations from spin to spin.
.
Yeah. In those days, each OS assumed that it owned the world, and would stomp anything else. It was not by intent, at least not initially, because nobody was trying to implement dual boot, in turn because it would be pointless, as each OS was written to a specific instruction set architecture. The emergence of UNIX undermined that simpler world.
Joe Gwinn
It sort of is - but is meant to not be tied to a specific architecture. And it lets me do a lot of things I haven't seen done elsewhere (so I implemented them into my tool when I needed them). Has my life been/is it "the horror"? Probably.
I had a similar wartime story some 20+ years ago for the Philips coolrunner. I thught I had all the data to write the logic compiler for it so I designed it in. Then discovered they had not given me the multiplexor data... good luck doing it without that. So I wrote a tool and multiple simple sources for their tool and from the jedecs they generated gradually deciphered the multiplexor. Took me about a month of work... I think I still have that mux decode data online, let me see... I do,
I meant any progammable part.
RL
remote sense is not paralelling. No idea where the FPGA logic is needed.
Got any old Condor or Power-One catalogs laying around?
I didn't think it was. But power supplies can be parelleled, in which case we'd only use one remote sense pair.
The FPGA will input from the voltage and current sense delta-sigma ADCs and generates the gate drives to the isolated forward converter. It closes the feedback loops and reports the voltage and current to the system. It will do safety shutdowns too.
We'll do cv, cc, programmed impedance, and programmed coordinated slew rates. Things like that. It can manage paralleling two supplies too.
No. I was hoping somebody would have some ps schematics with approaches to remote sense.
mandag den 4. april 2022 kl. 23.13.29 UTC+2 skrev John Larkin:
About all that the text says about remote sense is that it has it.
Do you understand the rs in the schematic, sheet 121? I don't. Seems like the diffamp gain changes when the rs is connected. That would be inelegant. Those giant diodes look ugly too.
The usual place to look for such details was the HP Journal; these are all online and freely available these days, at the Agilent or Keysight web sites.
The other classic source was US Patents. Usually, the names of the HP Journal article had much overlap with the list of patentees. So, given a patent, one can search the HP Journal.
Joe Gwinn
You could swap out the diff amp for an instrumentation amplifier, so you wouldn't lose any precision. Then the resistors between the outputs and the remote sense pins could be even bigger values and you wouldn't have to worry about them blowing up. There should be some instrumentation amplifiers with 42V common-mode range.
And what are those "RV" components at the output? MOVs?
On a sunny day (Mon, 4 Apr 2022 14:51:51 -0700 (PDT)) it happened Lasse Langwadt Christensen snipped-for-privacy@fonz.dk wrote in snipped-for-privacy@googlegroups.com:
page 101: Interesting big thyristor as over voltage protection across the output. Maybe John L. also needs one?
Probably not. An isolated switcher can be cut off several less dramatic ways if the voltage goes too high. It doesn't have the failure modes of a linear supply. For example, a shorted mosfet doesn't make the output go up, it makes it zero.
On a sunny day (Tue, 05 Apr 2022 07:08:32 -0700) it happened snipped-for-privacy@highlandsniptechnology.com wrote in snipped-for-privacy@4ax.com:
True, but I have seen other things go wrong reference voltage for example. And if you control it digitally with an FPGA or whatever programmable device anything can happen. It is a case of the value or danger of what is connected to it, in case of a spacecraft if it blows up something essential for survival.
I know :-)
But we can build in a lot of crosschecks that wouldn't be practical in an analog supply. A crude redundant output voltage measurement wouldn't hurt.
FPGAs don't seem to have random logic failures, like a board full of discretes can. They seem to work or they don't.
We'll mostly be testing aerospace stuff, which is the only reason we want to make power supplies. I might design the supply so it can't possibly make more than 36 volts, which is the danger limit for a lot of this stuff.
Popeys's statement is important and profound. Everybdy has to figure out what they are and be content with it.
Yes, provided that isn't used as a justification for not bothering to improve oneself where improvement could reasonably be made.
As with a many English laws, I leave it to the "man on the Clapham omnibus" to define "reasonable".
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