remote sense supply

The remote sense function is bound to be slowish, so you might just digitize and do the sanity check in software.

Cheers

Phil Hobbs

This is brute force:

I just let the FPGA kids worry about the ugly details.

I resent adding the upper isolated ADC, but it's pretty useful to detect gross mistakes and shut things down. I guess there could be other ways to do that.

The current limiters need to be wimpy enough that they don't push big errors into the remote sense wiring, but low enough that the ADC loading is small. Depletion fets maybe. Possibly power resistors.

Why FPGA? Why not some uC?

I could dump the upper ADC and sense voltage drop across the current limiters as the sense connection fault condition.

That ain't bad. Users would have to keep their wiring drops below about 1 volt, which isn't unreasonable.

Every plugin board in this box has an FPGA. We need to do a lot of signal processing. The isolated ADCs are ADUM7703 delta-sigmas with a

20 MHz bit rate, which need a heap of decimation processing. We'll do some 100 Mbit communications with the motherboard too.

The little Trion FPGAs are about $10. We could even run a riscV processor inside.

" The supply should work normally if the rs pins are not connected."

That, as written, worries me a bit. Its a bit vague, certain too vague to tell the customer, IMHO. Let's say by "connected" we really mean "the customer has taken steps to make the physical connections", therefore presumably the electrical connection as well. So I would insist the customer use your sense cable assembly (under terms of warranty); and your sense cable assembly has either a simple loop-back connection or positive-action mechanism that tells the FPGA/uP "the customer is correctly using this sense cable" and power may be delivered.

lørdag den 2. april 2022 kl. 07.03.16 UTC+2 skrev Rich S:

I'd take it as; the supply should output the correct voltage (just with no compensation) if you don't connect the sense wires, just like any lab supply with remote sense

resistors from output to sense takes care of that, but they need protection in case the output wires gets disconnected or the sense wires are shorted or connected in reverse

a sense cable assembly won't protect against bad connections or wire damages

For single-fault abnormals, you'd best resort to a power or logic crowbar/OVP, sensing main terminals. The sense linkage to the rail closest to reference ground may need a diode bypass to that rail. That linkage also has a lower R limit, for transient response.

Paralleling is a separate issue.

RL

Sounds pretty obvious to me. Don't use remote sense and it works like a simple power supply.

Let's say by "connected"

Remote sense power supplies are common. People seem to use them OK. I don't know if rs power supplies have any sorts of protections against wiring errors. I think some just have 50 ohm resistors from outputs to the sense pins. I posted to see what people know about that.

My customers make long custom cables with exotic MIL connectors. I sure don't want to do that for them.

I just want to be sure that nothing nasty happens if the rs connections are made wrong. We'd just shut down for a second or two and retry, and blink a red LED during the shutdown.

Thanks for mentioning these Trion FPGA-s, they look very interesting to me. Do you have any impression on their software licensing? I saw they sell it at $35 but does it turn into yet another subscription after some time?

I'll ask my FPGA guy. I get the impression that it's not bad.

They look cool. They are simple, with no ADC or high-end serdes or things like that. They do have a dram controller (I think), lvds i/o, schmitts, and a soft core riscV. 1Mbit of sram.

We're about to make a test board that includes the T20F256C4. We plan to measure a lot of stuff: pin-pin delays, Fmax on counters, LVDS common-mode levels, delay-vs-Vcore and temperature, jitter, drive strengths, things like that.

We asked their support people about some details of using the LVDS receivers at other levels, and they said "don't do that."

I might make an ADC using an LVDS receiver as a comparator. The minimal ADC would use three fpga pins and one external RC. That could be v-to-f, pwm, delta-sigma, or single-slope. Fun.

We've designed a flash manager with bootstrap and field upgrade and such.

I am only after standard functions, and if their lvds will do for hdmi video out I'll be happy. What I feel nervous about are their design tools, looks like they are just $35 for now but how quickly can they become prohibitive for someone who does not sell millions of units.

I never understood why FPGA vendors should charge for tools or use insane licensing stuff. Makes more sense to just give it away, maybe charge for support.

For many years - >20 - the electronica industry has been closing things down so only "politburo members" can do real development. Probably this is part of the same effort, FPGA vendors are interested in selling more chips but their large customers likely give them contracts against guarantees the tools will not be available to everybody.

I wonder if the $35 tool one can buy now will work on a PC with no internet connection. Guess I have only one way to know for sure.

I'd bet it's an attempt to lock their customers in forever.

A have MS Word 2016. Now MS Updater nags me to convert to Word365, which is only by subscription. Strangely, Word 2016 is now developing problems.

Very good question. And companies who want to protect their critical computers and networks from ransomware attacks et al may well have an air-gapped system.

Joe Gwinn

Could be if it is a one time fee. Not sure what is in at the moment. But it started a long time ago so it is more likely to be the work of some 'visionary' to prevent the spread of knowledge which would cost them zillions. Look at how they closed down all things wifi, the first - prism or something - was documented etc. until it got bought out and hidden from there on. Even T10 started selling their documents many years ago... So far the rfc-s are not hidden, but for how long. Some Sauron seems to be be lurking in the shadows :-).

I am not concerned about our design critical stuff, it is all under dps. They got a foot in when xilinx bought the coolrunner some 20 years ago, we had a logic compiler I had written; the cpld-s we have now use an old xilinx tool, old enough to work with no internet.

Guess I'll try some of these (too?) new fpga-s out, once I have a working logic as I need it I typically don't need to change it for many years. They seem new enough to be yet preoccupied with how to change one time sales into subscription, guess we'll see. Their fpga-s look really good on paper for what I am after.

A common problem.

dps? Maybe Texas DPS?

I'd say that my system of the future is air-gapped, as it's too hard to keep up with the threat of the day, so all Internet-dependent tools are excluded from consideration, and see what happens. You may need to stop talking to the sales droids to convince them that you mean it.

War story: In the early 1980s the transition to UNIX operating systems and computer platforms began. I was assailed with sales teams trying to convince me that their proprietary computer platform was so much better than those UNIX toys that no real man would consider UNIX. My answer was to take them on a tour of a storage room that was piled to the ceiling with the boxes that a few hundred UNIX computers had came in (being saved for delivery to the ultimate customer), and intoning that this was the future. None of those proprietary vendors survive.

Joe Gwinn

No, it is the OS run here, written/built on over the years by me.

Just did a shot of what my screen can look like (usually not as cluttered):

I don't have the muscle to make them change policy so I try - have been doing if for nearly 30 years now - to just be independent on software written by anyone but me. The one thing in our products we cannot reproduce without a wintel PC is a jedec file for a coolrunner CPLD, xilinx would not disclose its insides (we had a tool for it while it was Philips). Now I guess I'll settle for using someone else's fpga tool... Once I have the binary and a supply of silicon - which in our case it not large at all to be even a lifetime supply - I'll still have things under control I guess.

Well unix is a huge thing of course, most of the internet protocols have been done under it etc., but I am no unix person. When I have to use a unix command line I manage just the basics, if man works it is better... I remember some 10 years back I was trying to make a laptop dual-boot (xp and linux) and sector 0 was constantly polluted. Luckily I had made a copy of it prior to that using a boot CD and dd... :-). Was nicely surprised you could do such things not only under dps (it is not called dd there, just copy to device in non-file mode, does the same).

Just be aware that the trade-off with these i,s yes they are cheap and low-power, but they're that way because they don't run enough mask layers to provide much interconnect. The tools use LUTs for routing when they run out of very limited interconnect, and whether that consumes an unreasonable proportion of the chip depends on your signal flow and floor planning.

CH