ZCD with no Dflops

Yikes, the PEs are completely asynchronous to the clock. There's all sorts of available pathologies.

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John Larkin, President Highland Technology Inc

Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

Clue, like reading the table on the first page of the datasheet? Clue, like looking at the internal logic diagram?

You are violating the setup and hold times specs for both PE and CE inputs, and doing that across cascaded chips to boot. This *will* screw up, and won't take long to do it... just long enough to be a maddening intermittent failure.

Next thing you'll be claiming is that you designed this horrible asynchronous mess on purpose to annoy people.

Consider this: the comparator output is low, so CE is true into U6. U6 and U2 are happily counting clocks.

Suppose the U6 count is 0xF, and U2 is 0x4. U6 carry out is true (low) into U2. The correct next count would be Ox0 and 0x5, which is 80 counts decimal.

Now let the comparator output go high, so U6 no longer sees a true carry input. But it takes a while before the "don't count" Cout/Cin signal propagates out of U6 into U2. Clock it then. U6 doesn't count, but U2 does. The next state is U6 = 0xF, U2 = 0x5, 95 decimal, which is bad wrong. Classic carry chain error. U9+U7 have the same issue.

It's much worse if you consider what happens *inside* the chips.

Once you do async stuff, and violate the data sheet requirements, all sorts of hazards become possible, and you have to identify them all and prove that none of them will break the logic. That's hard.

"At that moment?" Wrong yet again. The PE from U3 to U7/U9 is 1.4 us wide, and it's an async DC jam load. When U6 and U2 count wrong, as noted above, the bad count is settled after a typ delay of 200 ns after the clock, and that's what gets loaded into U7/9.

It's a hairball. You don't get hazards like this in a clocked synchronous system.

No, it's combinational. Look at the chip schematic.

You have broken the synchronous nature of the carry chain - and of the counter's internal logic - by feeding U6 carry in from the asynchronous comparator output, splattering asynchronous levels all over the place. You are doing this just to be peverse, to prove somehow that hairball logic is a good thing. Jim approves.

You are treating the PE inputs of the counters as if they are edge triggered. They are not. If you assert PE for 1.4 microseconds, what gets jammed into U7/U9 is what's at their inputs at the *end* of the

Nope. Jim has no opinion, since I am not a logic designer and never claimed to be.

I do approve of Fields jerking you around, though it's getting tiresome. You are indeed suffering from brachycephalic rectumitis (otherwise known as "with big head up butt" :-), and seem hell-bent to dominate this group, preventing all real circuit discussion... claiming nothing can work but what you scribble (and fail to prove).

So I'm contemplating pulling a Woodgate and giving only advice on the LTspice group where it'll be appreciated.

=============================================================== || || || I'll also be available, when time allows, to help people || || who wish to contact me privately... use the "Envelope" || || symbol on my website. || || || ===============================================================

See! You even go out of your way to prove that you are fully infected with brachycephalic rectumitis (otherwise known as "with big head up butt" :-) ...Jim Thompson

You and JF constantly mention things anal and penile. Enjoy!

I _do_ enjoy you being caught with your head up your own butt, but you no longer exist. Bye. ...Jim Thompson