Re: Simple Count down Timer Project! New post!

Making design mistakes is not an indictment of the parts used.

They don't _appear_ on the circuit diagram, which is my point. From the schematic diagram, you can't tell if the PLD is a sequential state machine, a PRBS generator, or a brick. That's only transparent if you're clairvoyant.

Sure, flexibility is a plus. For some things, it's easily enough to make it worth taking the cost hit. That argument applies *a fortiori* to PICs, though, as opposed to CoolRunners.

In any case, that wasn't your previous argument, which really consisted merely of scorn and insults about 'legacy' this and 'amateur hour' that.

I don't recall ever having had a problem with MSI parts, even building high performance satcom PLLs with them back in the early 80s. They just work.

And in 10 years, that's even more wart-encrusted than the parallel port thing in my example. You're arguing my side again.

Did you look at the datasheet? The 4017 has one-of-ten outputs, no decoding required--it's designed exactly for sequencing. (It's particularly nice for interleaved control and data acq, which is hard to do well with analogue I/O cards.)

Sure, but you were arguing for using CoolRunners vs. 4020s. In any situation where a 4020 would work, you don't need any of that foofaraw. You're just trying to move the goal posts.

Indeed I have (for which I am forever grateful) but not in that way. I've very rarely designed two gizmos that were closely related, spaced one after the other. It's quite true that you can get into a rut doing that, especially working for PHBs. I've seen a lot of smart people get the creativity flogged out of them that way, especially in semiconductor manufacturing, with its constant atmosphere of crisis and what-have-you-done-for-me-lately. Fortunately I've been able to avoid having that happen in my immediate neighbourhood.

And none of that is an argument for using fancy-schmancy CPLDs to replace a jellybean ripple counter, however.

That isn't a counterexample. It may be an example of the opposite error, I don't know. What people say on Usenet and what they actually do are often pretty different.

Sure, I've argued exactly the same thing in print. It's like car repair--you spend some of the money you save to build up a nice set of tools.

The instrument literature is pretty famous for being dowdy and out of date--not to be insulting, but when it comes to professional publication, an instruments paper is a poor relative. I've written exactly one in my whole career, which was a little short thing on stabilizing high voltage supplies for driving piezos in tunnelling microscopes. (You float the supply, sense the hot end via a cap, and jiggle the cold end to compensate. The crowd gasps.) ;)

Any pickup and ripple and crap from a PWM isn't going to upset a feedback loop whose bandwidth is 1 Hz on a good day. You'd have to be pretty unlucky to have any AC spur component hit a bandwidth that narrow. Upsetting the thing that you're actually trying to stabilize is another matter, however.

That's particularly important in the present case, where the most sensitive measurement of the laser stability we have available is the performance of the sensor itself. That situation isn't particularly rare in high performance measurements.

You didn't read what I wrote. It's a laser locker, so the op amp isn't measuring temperature, it's measuring cavity reflection and transmission. I don't care what the temperature is, just the wavelength. (I don't even measure the temperature in the inner loop.) I know how close it has to be from first principles, but it will walk around a bit to correct for low frequency fluctuations in the laser.

Nonsense. You're using a private vocabulary, in which "fashion and prejudice" comprise all the inputs to a design decision.

Design is an art rather than a science, it's true, and since there are usually lots of ways to get something done, the personality and experience of the designer have a big influence. However--and it's a big however--there's a powerful feedback loop: cost and performance. As I said, it's engineering, not fashion design.

'Legacy.' Pshaw.

Cheers

Phil Hobbs

Not exactly. But design is like programming - you have to figure on the equivalent of one drop-off per thirty lines of code, and the less detail you need to plug into your design, the less chance you have of making a drop-off, and the more chance that the review process will miss that drop-off.

They are only transparent if you document your work. A schematic diagram only documents the connections, not why you made them. Some of the schematic diagrams I worked with included PROM memory maps, but these dated back to the days before computer-aided design, when the compamnies I worked for had relied on drafting film as the archival medium and dye-line copies as the distribution medium - even then we had to write up the design and the secretaries would type out what we had written, though that goes back to the 70's and early 1980's.

For the jobs that PICs can do.

The OP's "simple count down timer" is an amateur night design based on legacy parts - the 555 oscillator and the 4020 ripple counter. He isn't relying on parts he's familiar with, he's recycling ancient parts because he doesn't know any better.

They did get better during the 1980's, but the out-of-spec HP opto- isolator would have been aroound 1987.

You pin-for-pin replace with something that isn't wart-encrusted. It isn't as satisfactory as redesigning from scratch, but it's usually a lot faster.

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I don't to read the data sheet to tell you that the 4017 is a twisted ring Johnson counter. State machines don't usually let you get away with ten outputs, each of which is only high in just one state - typically you have to OR some of the outputs together to get the outputs that you need, not a big deal if you don't need to OR more than four outputs, and only slightly messier if you need more, but it still fals well short of a single chip solution.

Like I said, neither a 4020 nor a 4017 is a single chip solution. A handful of logic gates represents another kind of foofaraw. You've fixated on the foofaraw that you didn't master at your mother's knee, and ignored the foofaraw that you do know how to deal with.

Using one dead-boring PLD rather than an ancient jelly-bean ripple counter and a handful of glue logic does have its advanatages.

I get the impression that John Fields spends most of his time programming PICs, but doesn't much like talking about it.

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I've noticed - and published some five comments in the Review of Scientific Instruments over the last thrty years which have all said pretty much the same thing.

Op amp input have an unsavoury habit of responding to frequencies above the bandwidth of the feedback loop in a way that looks very much as if they are rectifying them - you need more than about 20mV of noise at the input to mess up a biploar input, and closer to a volt to mess up a FET input, We've all been cught by it from time to time.

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Yhe op amp isn't measuring "cavity reflection and trasmission". It's measuring a voltage which happens to be related to "cavity reflection and trasmission", presumably by a light intensity which you are measuring with a photodiode of some kind. Reading what you wrote told me absolutely nothing about what you were actually doing.

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They don't, but they do have a powerful influence. Think about "not invented here".

The good thing about the instrument literature is that people analyse what they are doing and why they are doing it. The bad thing is that they don't know much about the various possible ways of doing it, and fixate on the first solution that they run into that works.

As long as you are playing with stuff that you've inherited from yourself, you don't notice that your inheritance lost its lustre a few decades ago.

-- Bill Sloman, Nijmegen

And that about sums it up, I agree.

Cheers

Phil Hobbs

I saw that the 1.8V ones were cheaper, but then you have to put in level translation to talk to anything but more 1.8V logic. I specified VDD >=

I've actually never needed to use a CPLD bigger than one of the oversized 22V10 variants, but then I'm not a hard-core digital hardware guy. I mostly use stuff like that to get really low jitter sampling and to interleave control and data acq accurately.

(Anyway, we've about flogged the cover off this dead horse.)

Cheers

Phil Hobbs

Coolrunners all have 3.3V I/O. If 3.3V is all you have, add a dime for the Vcore LDO.

I'm using a Coolrunner for this primarily for space (and manufacturability) reasons. The board is only about 3/4"x3/4" (fits in a DE-9 backshell). The cost isn't important. Yesterday I learned that C32 is too small for the application (requirements change) so I'll have to go back and find the next smallest device we can place.

You think Slowman knows it's dead?

Good to know--I may have to try one out for grins. I used to use Orcad PLD for DOS, which still works fine for small PLDs of antique type like the 22V10. Do you use ISE or something else for designing them?

Maybe the next-smallest-but-one. ;)

Cheers

Phil Hobbs

The Freebie ISE stuff. Seems to work fine for simple projects (divider from

Indeed. I may have to throw the 422 driver overboard and use the Coolrunner I/Os. Wouldn't be a problem if the CPLD had clocked I/Os.

I've used PICs since the 16C54 in about 1990. I can still make it.

That's what Rich understand of the debate, making it clear - once again - that he doesn't begin to understand what the discussion is about.

-- Bill Sloman, Nijmegen

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Roughly equivalent to to someone saying that they never use anything more recent than a 741, but they aren't hardcore analog hardware guys. So the 741 is older than the 22V10 which is turn ia few years older than the ICT PA7024, but even twenty years is a long time, and PLD's have come a long way since then.

For really low jitter, I'd have imagined that you'd be looking at PLD's with LVDS - low voltage differential - outputs, which can drive terminated balanced 50R transmission lines without burning a hole in the printed circuit board. The last time I was seriously interested in fast PLDs was more than ten years ago, but LVDS I/O did seem to be the flavour of the month back then

Xilinx Virtex-E parts do seem to offer this as an I/O option. They don't seem to be low-power parts, but really low jitter is incompatible with low-power operation.

-- Bill Sloman, Nijmegen

Virtex-E was over a decade old (I used them in '99). Crap, they're up to Virtex-7 (six generations later). Pretty much every FPGA, today, and a lot of CPLDs (sorta) support LVDS now. Coolrunner is the obvious exception, perhaps because they don't have registered I/O. Even low power parts (everything is lower power than antiques like Virtex-E) have LVDS I/O.

Sloman doesn't even know that HE is dead.

And if they're not brown it's only because he's a quart low.

G=B2

Oh, he's always as full as he is wrong.

There's not enough laxatives in the world for that to ever happen. :(

And krw knows just as much about the one as the other - absolutely nothing ...

-- Bill Sloman, Nijmegen

Nothing about being full of it, or being wrong? Why thank you, Slowman! I didn't know you cared.

Guys, I am an electronics engineering major student, I love posting new circuits that works well. I am willing to learn new things from all of you in this forum. Thank you..