>> Does anyone know anything about the effects of negaive-voltage
>> zenering the gate of a SiC power fet?
>>
>> Specifically, I'm designing a gate driver for the Cree C2M0280120D and
>> I'm wondering about what might happen in the rare case that I zener
>> the gate by a mA or so. The intent is to drive it -5 to +15, but the
>> -5 could be more in some pathological case.
>>
>> I'll get some from stock later and test some, but that's necessarily
>> short-term. I have seen long-term changes in some Gan parts from
>> abusing the gate a bit.
>>
>> googling hasn't helped.
>
>What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:
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If I change one dc/dc converter, I can make the -10 into -24, which makes things nicer. R1+R2 can get bigger, which helps when they have to go from 5 to 500 volts across them.