power supply dynamics

That's what I'd have to do if I take the feedback from the output, like power supplies usually do. The loop would be crazy slow.

One nice fat low ESR polymer output cap would be great in a power supply, but the loop dynamics would be terrible with the fb from the output.

Post-filter feedback controllers that have good performance don't need a PhD:

Since you're using a FPGA anyway do you even need to low-pass the switch node voltage in analog and send it to an ADC first?

Since you're pre-filter anyway I think you could just level-shift and send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as your "1 bit ADCs" if you will

The other issue is that we don't know what the customer load might be. It could be capacitive, or inductive, which would change our loop dynamics.

I suppose I'll have to Spice this. Whatever analog loop I come up with, it can be done in the FPGA.

Just to take out any really fast spikes.

The FPGA is driving the fets, so we know their state. The +48 could wander a bit, and it doesn't know that.

Your 'tweak' , even without rcfiltering, is expected to be faster than simple feed-forward compensation?

That is preposterous.

RL

Ah, gotcha, I see the UC27712 is just a driver. The current shunt post-filter also makes it easy to detect shorted loads.

I think wandering at the switch node could be detected by a current sense amp there, too, if there's no net current going in or out of the cap then I don't think it can be wandering. It might be possible to save an ADC channel that way

Average current-mode control has a lot of nice properties:

It's not a preposterous idea to take the feedback from the switch node and math out the droop at the output.

With the inductors I can get, I might lose half a volt at full load. I'll know the current so I could cancel, say, 90% of the droop.

Compound fb wouldn't be too hard. Get the AC feedback from the switch node, DC fb from the output. That might take two more parts.

But, typically a power supply is a voltage source, with some droop allowed at the highest currents (and certainly in the presence of transient current draw).

So, do you intend hard shutdown (foldback) on overcurrent, or lessened regulation when past a threshold, or just blow a fuse? You can't kill all eight power supplies trying to get more power into the one that's reached its limit.

As for fancy regulation tricks... keep it simple, just use a voltage reference instead of a power supply, when the last 1% ripple in voltage matters.

Sure, but I'll be measuring current and can cancel most of the droop for free, asuming that VHDL code bunnies are cheap.

Each one will current limit, or maybe some combination of current and power limit. If each supply can output, say 40 volts max at 0.5 amp, we could allow them to make 5 volts at 1 or 2 amps. The limit there would be the D-sub connector pins, which are variously/randomly rated at 1 to 2 amps.

My customers buy power supplies. Being in the aerospace business, they are used to their DC supplies being really ratty, with long cable harnesses, so this supply doesn't need to be lab quality or have remote sense.

One feature they want is simulated timed open-circuit, which is easily done by turning off both fets in the helf bridge. They don't care about isolation!

lørdag den 1. juli 2023 kl. 16.23.12 UTC+2 skrev John Larkin:

most datasheets I've seen says 3A or 5A per contact

The ringing is from the passive L1-C1 thing, not the loop. Some damping could be added across C1 to kill the Q and beautify things some. I might do that if there's room on the board.

Next step will be to hack in the real switching half-bridge and tune things.

This is cool. The error amp is a simple integrator, which shouldn't challenge my VHDL code bunnies to implement. Taking the AC part of the feedback from the switch node is beautiful for dynamics.

Now it needs a current limiter and the actual switching bit.

Does this link work?

Yes. Ed

Sampling the switch node is giving you information about the supply voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to be much lower than inductor loss and inferable from current measurement. For DC accuracy you most likely will still need to sample the post LC output. For your AC dynamics you might as well just sample the raw supply voltage?

piglet

Here is is:

One nice thing, in a power supply, is that it behaves pretty well no matter what crazy things the customer may connect it to.

Many power supplies try to solve that problem by having huge output caps, which make giant sparks when the supply is shorted, no matter what the current limit is set to. I won't have room for giant caps anyhow.

That LTC driver is supposed to have shoot-thru protection, but the top fet was frying in simulation. We'll actually use the TI driver, and our FPGA can add shoot-thru timing if we need it. The actual control loop will be all digital.

One sim run like in the pic takes maybe 20 minutes. I had lunch and hosed out the garage during runs. Maybe I need a new PC.

It's hard to tune a control loop with 20 minute feedback.

What is the 48v supply impedance, can’t see the series resistance of v6? piglet

The 48 supply is a kilowatt MeanWell switcher, and I'm assuming it's a perfect voltage source. These will be relatively tiny supplies, ballpark 20 watts each maybe, so they shouldn't affect the 48v buss much.

And, as I tell people, it's just a power supply.

I actually see people putting bypass caps across voltage sources in Spice! It's sometimes hard to remember that we're simulating, that dissipating 20 watts in a pullup resistor doesn't matter, or that 50 ohm resistors are actually 49.9.

Well, sometimes we add stuff that's not sensible in simulation, as reminders about real life later. Like the gate resistors.