Re: Raspberry Pi pico2 launches with an ARM and a Risc V processor core

Aug 10, 2024 Last reply: 1 year ago 6 Replies


Raspberry Pi Pico 2 Launches with Arm + Risc V Cores: hands-on with the new, $5 microcontroller


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>So 2 processors for 5 $
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>Comparing some features
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> Raspberry Pi Pico
>SoC: RP2040, Dual Core Arm Cortex M0+ running at up to 133 MH
>SRAM: 264 K
>Flash Storage: 2MB QSPI
>3 x 12 bit ADC
>sleep mode < 100 uA
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> Raspberry Pi Pico 2
>SoC: RP2350, Dual Core Arm Cortex M33 or Dual Core RISC-V Hazard3 running at up to 150 MHz
>SRAM: 520 KB
>Flash Storage: 4MB QSPI
>Security: Arm TrustZone, 8KB OTP, Secure Boot
>4 x 12 bit ADC
>sleep mode < 10 uA
>
>More in the above link.

That's amazing. The Pi stuff is incredible.



We're designing around the RP2040 chip now. Dual-core ARM for 70 cents. It's rated at 133 MHz max, but overclocks to about 400. Some lunatic froze one and ran the core voltage up and got it to work at 1 GHz.



We're now designing an interposer board, to connect to a Pi 400 on one end and to a 20-pin ribbon cable, to our DUTs, on the other, for development and for production test both. I can post the schematic if anyone is interested.


It is strange to get a choice of CPU!

I'd expect that at the bit-bang level, performance will be about the same. On a 2040 ARM chip, we can bit-bang a gpio port and make a train of 7 ns pulses, which is single cycles with a 133 Mhz clock. RiscV can't do better than that.

It would be cool if the floating point ops were faster, in either mode. On a 2040, the usual single-precision things take ballpark 600 ns.

Almost certainly will be!

The 2040 uses an M0 processor core, which doesn't have a hardware floating point-unit. It has floating-point emulation libraries in the ROM.

The 2350 uses an M33 processor core, which has a single-precision hardware floating-point unit.

As long as your needs are met by single-precision floating point, and can recompile your code with floating-point instructions enabled, the

2350 should be quite a bit faster than the 2040.

For double they have an assist co-processor that speeds up parts of the operations with multiple instructions to do the operation.By using the assist processor for the core function they can significantly reduce the hardware while still getting a speed up since the rest of the code to implement the function needs fewer instructions than a full software implementation.

See section 3.6.2

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haven't you been designing that for years now? trying to out do Slowman? :P

I've been thinking about a new product line for a year or so, but I'm now hiring engineers and doing the first PCB layouts to make it real.

I had some other projects to finish.

Outdoing Sloman is a mathematical dilemma, dividing by zero.

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