New ISA board to play with transputers

In a previous life I had quite huge a T800 Tranputer cluster and also did some designs that connected to it. The ISA bus was not important, but there was a link adaptor chip (C11? - where is my bottle of Gerontol Forte?) that had a SRAM-alike "foreign" side that made it easy to handle.

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the link chip is between the Western Digital SCSI controller and the VLSI serial/par IO chip.

Complete industrial PC/AT with Multibus2, lots of DRAM, disks, floppy, ... Thanks Goddess I had someone to do the board layout in DOS Orcad STD on a Compaq 286 :-)

Occam was fun. Maybe nowadays it would make a bigger impact with a substantial number of CPUs on a chip.

Cheers, Gerhard

Like an XMOS chip perhaps?

These seem to have been developed by a team that was originally involved with Transputers. John

This is very much legacy electronics. The transputer was a nice idea when it was invented, but there are now (and pretty much always were) different and better ways of solving the problems it addressed.

Since CPU cores are trivial nowadays - they cost a few cents each - the transputer concept may make sense again. We rely on an OS and compiler tricks to get apparent parallelism, and the price is complexity and bugs.

Why not have a CPU per task? Each with a decent chunk of dedicated fast ram?

So all tasks are created equal? And dedicating a CPU to every last one of them isn't an over-kill for most of them?

Parallel processing and multitasking are both a complicated subjects, and one-size-fits-all-solutions don't seem to exist.

People who do special purpose electronic design do tend to have a grab-bag of techniques developed to solve other problems for other customers - John Fields could solves lots of problem with a 555, but my feeling was that a lot of his solutions were sub-optimal.

Great job!

My agenda includes mastering kicad 9 - including its interface to ngspice - as soon as possible. My passion these days is exploit Zynq

Danke,

Intel tried that:

The issue is one of memory capacity and bandwidth. Many applications have a large (GB) dataset that doesn't partition nicely up between multiple nodes.

Even the largest FPGAs tend to have MB-scale amounts of memory on them, not GB, because the memory density of a dedicated DRAM chip is so much better than making on-chip BRAMs. It turns out to be more efficient to use a large external DRAM and drive it in a highly parallel way, pumping data through a GPU-style core, than it is to have lots of little cores individually fetching single words from their local BRAM. With that model you also need a fabric for the little cores to communicate, while with a big DRAM you get inter-core/thread communication for free - you just arrange to a write to a different part of the shared dataset and the next consumer picks it up.

You can of course put GDDR or HBM on an FPGA, but it's the same problem - only a few devices must be shared by numerous cores. Ultimately memory throughput beats latency hands down, especially for large datasets. This was not such a problem in the Transputer's day, which is why that architecture made sense.

Theo

Don,

You do need to use the center tap on TR2 to get anything but a sophisticated short circuit.

Seems a shame to have an x86 core wasting time handling ethernet and printers and mice and memory sticks when they could be doing better things like running Spice.

My Windows 11 thing is running hundreds of processes right now. That's crazy.

Computing is a mess. A new hardware architecture would at least suggest a fresh start.

The schematic is a work in progress. Its 100 ohm load resistor is missing along with terminators for the Local Oscillator and Radio Frequency inputs and Intermediate Frequency output. Oscilloscope outputs from the ADAML2000 and a Tektronix now appear at my webpage:

The LTSpice simulation in AD's tutorial looks great. AD's practical circuit, as shown in its tutorial, leans a little towards a "sophisticated short circuit." Ergo, the motivation for my webpage.

Danke,

Many of those things are already happening outboard anyway - all those things have processors in them. What the CPU is doing is largely managing the data transfer to and from the device. eg the printer speaks PCL or Postscript and the OS's workload is limited to firing the job at the printer (USB/network) and the printer's CPU then decides where to put the ink on the page.

You can delegate that management oversight to another core if you like, but then you need management oversight of *that* core.

Windows problems :-) But many of those things don't need to take much CPU - they're ready to handle print jobs when you press Ctrl-P, but the rest of the time they're ticking along in the background not taking much resources because they don't need them.

The OS is running thousands of kernel threads, but they're mostly blocked (not scheduled) until they need to do something. One thread per 'thing', more or less. All that thread needs is a few hundred bytes for its register state so the impact is small.

Non-Windows, non-x86 architectures are available...

Theo

The x86 is nearly the peak of the silly concept that the CPU is a big deal. Intel is heavily invested in that idea. ARM and Risc-V cores are fast and cheap and basically trivial amounts of silicon. We can have a zillion CPUs on a chip so don't benefit from the brutal complexity and inefficiency of trying to share just a few big ugly CPUs among hundreds of processes.

We use the RP2040 chip in some products. It's a dual-core 133 MHz ARM with lots of cute peripherials, including hardware state machines. It's 75 cents in any quantity. On the new version, the RP2350, they threw in a couple of RISC-V cores just for fun.

Maybe "just for fun" but it might give them a stronger position when negotiating royalty rates with ARM. John

Yes, my thoughts too.

I wonder how much they pay to license the ARM. It can't be much, with two cores on a 75 cent chip.

Intel stock is at about half its peak. Market cap is $101 billion.

Nvidia stock is at an all-time peak and worth $3.9 trillion.

CISC is *so* last millenium.

The transputer doesn't offer any value actually. I only did it to re-run my old software, and because I had curiosity about running Occam. Installing Occam and trying to get things runnings was not a so amazing experience as I expected.

Once the Pentium was out, the transputer was basically obsolete.

It is my first "complicated" circuit board, so I didn't want to munch more than necessary.

The ISA is an important asset, because there's no point on putting a transputer board on a Pentium machine, but I have a 80286 where the transputer speed is obvious.

Regards,

I get now your point. I never thought about it. But I published the schematics in case someone wants to do another type of interface.

The multiplatform ability currently is my transputer emulator in Javascript. It runs on PC, Mac, or Linux, just visiting my webpage at

Maybe it could be a mathematical coprocessor for Arduino, but it would be too expensive.

Regards,

This doesn't take into account the architecture of the CPU. There is no need to dedicate a CPU to task, because multiple task can be mapped within one CPU.

The nodes in a parallel system, shouldn't be low level but at a par with the most cost effective CPU in the era. There was no investment in a 4 Ghz T8000 (64 bit) with 1 Gbyte links and I bet that it could have at least have a niche for itself.

I was involved in a geology simulation system with interactive graphics for the Shell (1990). The alternative was the Cray, and the difference in costs were staggering.

I made a twin counting program as a demonstration. We (HCC) had a heterogeneous bunch of in total 60 transputers. I borrowed from military and educational institutes for a total cluster of 180 transputers. They worked well together, a hotspotch of power supplies and transputer boxes. Imagine 180 386 boxes working together.

I'm firmly convinced that the transputer route is not fully explored. HuaWei beats nvidia with ai, not with superior cpu's (although that is coming), but with superior inter cpu communication.