Radiated Emc ethernet problems

I have just designed a prototype Arm 9 based board that uses a Davicom DM9161 ethernet chip operating in RM11 mode, basically it require a external 50MHz oscillator that feeds it and the MAC in the processor. The board has just failed EMC emissions at 50MHz and 100MHz which are due to the ethernet, disconnectioning but still running the 50MHz ethernet oscillator made it pass. We have the option on the redesign of using MII ethernet mode, which uses a 25Mhz crystal into the DM9161, though internally a 100MHz clock is still required, the communications to the MAC is then at 25MHz (100Base) and comes from the DM9161 TXCLK and RXCLK. Would you expect doing this would reduce the EMC emission problems at 50 and 100MHz? Thanks for any advice

Steve jones

Reply to
sjones
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I read in sci.electronics.design that snipped-for-privacy@scannex.co.uk wrote (in ) about 'Radiated Emc ethernet problems', on Thu, 15 Sep 2005:

If your Ethernet cable is radiating, it must have common-mode signals on it. You can get rid of those by proper board layout and other well-known techniques, such as common-mode chokes and ferrite rings.

If you just alter the frequencies without correcting the cause of the emissions, you will very likely not pass again. Do you have Tim Williams' book on designing to pass EMC ('EMC for Product Designers' third edition)? If not, it could save you $$$$ or even £££ - real money!

Go to:

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with £32 and even get 1p change!

--
Regards, John Woodgate, OOO - Own Opinions Only.
If everything has been designed, a god designed evolution by natural selection.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
Reply to
John Woodgate

Not really. This problem probably has more to do with routing and filtering than with exact clock frequencies.

[snip]

At the risk of stating the obvious, you have to route the Ethernet traces as differential pairs, and take steps to keep common-mode voltage from getting on to the pairs outside the board. The two elements of differential pairdom are 1) keep a small constant separation between the traces, and 2) match them to the same length as closely as possible (say to 10 mils, or something like that). If the traces are long, you should strive to route them at around 55 Ohm characteristic impedance to the nearest plane. If you have some kind of trace impedance calculator, you can tell it that you want 100 Ohm differential impedance between the traces, and let it figure out the right width and spacing for you.

I believe several companies make magnetics modules for fast Ethernet (Pulse?). I think the standard technique is to use a transformer with a center tap on the primary. This center tap is shunted to ground through a capacitor. The magnetics need to go as close to the RJ-45 as possible.

I think there are also RJ-45 connectors with magnetics built-in.

When I used to work for a big company that had a LOT of collective knowledge about passing EMI the first time, they used a clean-ground philosophy on all boards. The idea is that around the periphery of the board, there is a band on every plane layer of "clean ground." Anywhere signals went off board, they were filtered right before "clean ground." Shielded connectors were also grounded to this clean ground.

HTH

--Mac

Reply to
Mac

I have the problem even when the EMC cable is disconnected. I have followed all of Davicoms EMC recommendation. I do have Tim williams book and have passed many products through EMC class B. The differential pairs are matched length, no vias and spaced apart. The DM9161 has a 0v and AVCC planes under it, derived from digital via ferrite bead from 3V3 and decoupled. Its a 6 layer PCB. Basically I have followed Davicomns recommendation with the exception that I am using RMII rather than MII. I am thinking of trying the Micrel chip KS8721 as they seem to have more consistant layout recommendations but I have the option of switching to MII if it will help!

Reply to
sjones

A 'board' can't pass or fail any EMC test.

EMC tests can only meaningfully be performed on 'equipment'. Meaning in an enclosure for one thing.

So, what was really going on ?

Graham

Reply to
Pooh Bear

This is similar to what I have done. Does this treatment extend to the

0V "signal" as well? I.e. is the 0V logic plane isolated from "clean ground" and connected via a filter?
--

John Devereux
Reply to
John Devereux

I read in sci.electronics.design that snipped-for-privacy@scannex.co.uk wrote (in ) about 'Radiated Emc ethernet problems', on Fri, 16 Sep 2005:

You mean the limits are exceeded even without the cable? Where are the emissions coming from, then, the power leads?

Well, even though you have tried hard to do it right, that common-mode (CM) stuff is getting there somehow. I don't know what you mean by RMII and MII, but until you find where the CM is coming from, you are likely to find that it happens whichever IC you use.

--
Regards, John Woodgate, OOO - Own Opinions Only.
If everything has been designed, a god designed evolution by natural selection.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
Reply to
John Woodgate

Could it be that ethernet is not compatible with the EMC standards? :)

--

John Devereux
Reply to
John Devereux

I don't remember if it is connected with a real filter or if it is just bonded in one place, but it is something like that.

Sorry I don't remember right now. ;-)

--Mac

Reply to
Mac

After reading the entire thread (with lots of coffee ;) , here are some things.

Even though the ethernet is routed as a differential pair, do you have any stubs for test points? Have you measured the impedance yourself with a decent TDR machine? (Do both single ended and differential TDR for best results).

When you failed, did you get a 3D polar plot for the emissions? That can help isolate where the emissions are coming from. Failing that, do you have a simple passive sniffer (there are schematics available on the net) and a spectrum analyzer?

Is the noise coming from the ethernet device itself? Is it properly decoupled? (You'd get clock noise into the power system).

Is your master oscillator noisy? I notice that for RMII mode, the XT2 pin is a 50MHz clock reference, rather than being able to use a crystal. (See datasheet pages 9 and 11).

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Did you follow the layout guide? (There are some here who would take exception to some of it's recommendations!)

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If it is fairly easy to switch to MII mode, you might give it a try. The only thing it seems to save in RMII mode is two transmit MII and two receive MII tracks, at the expense of doubling the signaling frequency on the remaining signals.

I would note that in MII mode, you can use a 25MHz crystal rather than an external 50MHz clock which is single ended by definition (at least at the input to the chip). If the routing of the clock is not dealt with in the same manner as other possible radiators (impedance controlled and terminated) you can expect emissions. You can also expect harmonics (which you seem to be getting). Apart from that, you reduce the signaling frequency on the TX[n] and Rx[n] tracks anyway.

Just something to think about

Cheers

PeteS

Reply to
PeteS

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