Question

The OP asked a very silly question, but this is an even sillier answer.

In practice via size is limited by the drill sizes available to create the via hole, and any practical via size gives you enough surface area that the copper layer laid down has very little electrical resistance.

With very high speed logic, you probably should worry about the extra induc tance inserted by the via, and make sure that the ground planes defining th e other sides of your transmission lines are properly linked at the via, so tha the return current flowing in the ground-planes doesn't have make a lo ng diversion.

You should not have holes in your vias. Holes represent a shortage of electrons and as such will capture passing electrons.

Cheers

Can we use them to fix what got broken?

Don't forget the skin effect, the high frequency current moves only very close to the surface, causing additional losses.

But does the current flow on the outside of a plate through hole (between metal and PCB) ? How about the inner side of the hole ?

Of course, with sufficiently high frequencies, the RF will pass through the hole in some circular waveguide mode :-) :-)

If it's for logic, then you only need to make the vias big enough that they'll get reliably plated. If the vias are plated with copper, the electrons will get through. How big that is depends on your PCB manufacturer -- consult with them.

Logic signals are low current, so any via that a board house can make will be fine. Vias are pretty good conductors. 10 mil drills (0.25 mm) is a pretty common signal-level via these days. Maybe 15 if the board's not too dense.

For really fast signals (edges below 50 picoseconds maybe) a via can be an impedance mismatch, so more care is needed. It's seldom a problem.

What do you consider "high speed" for this project?

You want friction so that they can reproduce..

"Ko"

Then you never have to worry about seeing electrons again.

.... Phil

I love Phil's answer!!

I was going to offer that the lower bound for the size of the via would be the size of the electron itself (otherwise, it wouldn't fit through!). :)

And then, the upper bound could be set by how many electrons can safely pass through simultaneously. For if they all fell through at once, there wouldn't be any left over for your circuit to work.

A multilayer, non-plated hole might be used as a tiny particle accelerator or as an electron lens.

How about you flood a PC board with electrons. Nonplated multilayer vias gate pixels onto a phosphor screen, the top layer of the board.

Or build a scanning electron microscope from just a PC board.

Or a plasma display.

Or a triggered spark gap.

Just try to snatch the pebble from my hand, grasshopper...

These days microvias are approaching minimum sizes seen in design rules from early IC manufacturing. 15um are apparently possible.

Aside from just saving space occupied by the annular ring etc., via-in-pad can allow you to fan out a big BGA with a smaller layer count.

Reducing the via diameter through a 1.5mm board from 0.5mm to 0.1mm increases the inductance from ~0.6nH to ~1nH-- pretty much negligible in comparison to that from typical trace lengths.

Best regards, Spehro Pefhany

The electron lens idea is probably possible, though it would put pretty stringent requirements on the roundness of the hole. Perhaps the hole could be burnished to be very round.

Microchannel plates get nice round holes from etching the soft glass cores out of a fused fibre bundle.

Fun. It would probably have a resolution of about an inch, but still.

Cheers

Phil Hobbs

the

the > > copper layer laid down has very little electrical resistance.

at > > the via, so that the return current flowing in the ground-planes do esn't

It's while since I read up on laser drilled holes, and back then they were always conical, and couldn't be more that fifteen times deeper than they we re wide. That's perfectly compatible with a 50um diameter hole in individua l layers of a multilayer board.

Getting that sort of aspect ratio out of plasma etching or chemical etching sounds more difficult, and expensive,

Well worth paying for.

Sure, but when you have to treat traces as transmission lines, you also hav e to worry about the extra inductance in the in the return path. Sadly, you can't often have your via flipping the trace from one side to the other of the same ground plane, so you mostly have to figure in the impedance of th e via's linking the two ground planes, often including the capacitors that allow the two ground planes to be at different DC voltages.

My experience with very fast pulse edges was that they didn't like vias and this was with a pulse which we could narrow down to 500psec wide. Modern " very high speed logic" can go a bit faster.

One SEM structure is just a circle of rods, maybe 6 or 8?, that the beam travels through.

Imagine a circle of vias, then drill a hole through the board, slicing each via in half. The drill hole could be tiny. Vias cut nicely.

Stack a couple of boards maybe. Cheap student microscope. The biggest problem is the electron source.

There must be something useful that you could do with PC boards beyond just soldering parts to them.

Blind vias and back drilling are the usual ways around that. If you do it right, vias are okay up to > 10 Gb/s, and faster if the runs are short.

Cheers

Phil Hobbs

We've done several Gen1 PCI Express designs now, 2.5 gbps and 80 ps edges. We used ordinary full-thru vias, no problems, sweet eye diagrams. Most fast data links are brutally actively equalized these days anyhow... pcb traces and cables are usually much lossier than vias.

The "return path" issue is more HoJo Black Magic nonsense. Parallel PCB planes are already huge capacitors and don't need help to be equipotential at signal speeds.

A via can be slightly inductive, so some people like to surround it with ground vias to keep a matched impedance in the vertical direction. But the prop delay through an 0.062 thick PC board is only around 8 picoseconds.

Backplanes can be pretty thick, though. There-and-back through a 4 mm backplane is 8e-3/3e8*sqrt(4.5) ~ 57 ps, assuming a TEM propagation mode. That's not such a worry for transmission, but the capacitive reflection from an open-circuited via stub can be pretty important.

Cheers

Phil Hobbs