I often add TDR test traces to multilayer boards, with layer-layer via jumps, traces crossing split planes or gaps in planes, stuff like that. The vias are no big deal on a 30 ps TDR, down there with the fiberglass weave. Skin loss in copper traces is a bigger practical problem. A lot of the conventional wisdom about this stuff (and about bypassing) is wrong.
If vias pass through planes with small annular clearances, they tend to be capacitive. I suppose that can be tuned by tweaking the clearances. I should try that some day.
1 ns edges are easy. Below 200 ps things start to get more interesting, but just pumping logic levels around a board isn't hard down to roughly 50 ps.