Hello,
Is anyone familiar with any techniques for reducing overshoot in the pulse response of a unity gain op amp follower configuration?
Thanks, Jim
--------------------------------------- Posted through
Hello,
Is anyone familiar with any techniques for reducing overshoot in the pulse response of a unity gain op amp follower configuration?
Thanks, Jim
--------------------------------------- Posted through
Need more detail! The simplest thing to do would be to put an RC filter ahead of the op-amp:
___ |\ o------|___|----o-------|+\ | | >-o----o | .--|-/ | | | |/ | --- | | --- '-------' | | === GND (created by AACircuit v1.28.6 beta 04/19/05
But this depends on your source impedance being controlled, or being guaranteed to be significantly less than your series resistance.
-- Tim Wescott Wescott Design Services
Yes :-)
Oh Lord, I apologize... I just couldn't resist ;-) ...Jim Thompson
-- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et |
What opamp, what swing, and what speed?
John
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If the overshoot is due to capacitive loading, you can insert a resistor in series with the output, but in the feedback loop. This is in the National apps.
If the amp itself has overshoot, I don't see any really good solution unless it is externally compensated. I suppose you could divide the signal by two and then set up the op amp for a gain of two. That would increase the phase margin.
Some opamps have diodes between the two inputs. Fun stuff can happen if you drive a follower faster than its native slew rate.
John
Here's some useful info. You might get away with just a snubber network on the output:
Mark.
lse
npacitiv...
Good article. I'd use figure 3. I think snubbing is trickier than the paper indicates. GBW has a tempco. Output stage "native" impedance is a function of load current. I just don't see snubbing being very reliable, though I have no first hand experience at this. Figure 3 is used in lots of DUT boards.
pulse
on
capacitiv...
That is nice. I've used the figure 3. circuit, but always found 'usable' values by mucking about. (While looking at the step response.) Do you know of a better reference for the derivation following figure 3? I don't quite get why I should equate the pole's and opposite zero's of the two circuit cases. C-f shorted and C-load open.
Oh for any reading along at home, I found it easier to rewrite the equation for Cf in terms of two 'times'. The output time Cl*Ro =3D To and the feedback time Cf*Rf =3D Tf. The remaining two terms are then the one with the loop gain. (something near one for gains above 5 or so) and (1+Rin/Rf) a bit more than one for reasonable gains. So except for a factor near unity, Tf =3D To. (And I'm still going to pick the cap and muck about... I just have a better starting value. Thanks)
George H.
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