...Jim Thompson | mens | | et | | | | |
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Thanks for all the links Phil, I was just checking on which 'flavor' my data is from.
So the data I took was for TI's 4046... and I now notice that someone in production purchased the more expensive NXP flavor.... grumble, I should go back and re-measure. (Why do people always have to 'piss a bit in the pot' and change things?)
George H.
I always wondered what the "phase pulses" were good for. If you don't need them, my 8-gate wonder* would do, and I don't think it has a dead zone.
-- Reply in group, but if emailing add one more zero, and remove the last word.
Taking note that I'm not a logic designer, I'm not sure your version covers all states. It took Ron Treadway NINE gates back in the mid-60's in the MC4044...
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Digital PLLs don't have the performance of analogue ones, and are far, far more complicated and power hungry. My usual use for PLLs is demodulation rather than frequency synthesis, so DDSes are pretty much beside the point.
You can get inductors in 2% tolerances, and the varactors of course are variable (and also good to +-5% to 8%), so you don't need tweaks to get a very respectable linearity improvement. That means that you can be more aggressive on the loop compensation, and the improved performance is worth a lot.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Wow, $35? I can buy a lot of good analogue stuff for that!
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
The phase pulse output is for lock detection. PD2's output is valid in any condition, and when using PD2, PD1 will have a 50% duty cycle when the loop is locked and also when one of the input signals is missing.
I normally just put a window comparator on the PD2 output and use that, since the filtered output pulls to the rail when it's out of lock.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
We have considered using a phase detector and a DDS, 100% digital PLL, inside an FPGA to be able to do i/q demodulation of digitized sinewave signals. It sounded like fun, but we never had a firm application (ie, paying customer) to justify doing it.
In one case, it would have been AC line stuff, 50 or 60 or 400 Hz, fairly narrowband (except aircraft 400 Hz is all over the place.) In another, it would be synchro/LVDT, pretty much audio kind of range.
The digital PLL takes no parts... it's just a heap of VHDL.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
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If you already have an FPGA, sure, dump it in with all the other crap. ;)
A good diode phase detector such as an MPD-1 makes it a pleasure to build first-class PLLs. Lots of output, zilch noise, low and stable offset voltage, easy to drive from logic if you need to. Good medicine.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
As far as I remember that's the very first time I disagree with you, but for this subject I do. A customer of mine builds world class analog DLLs & PLLs for special navigation and timing systems, but when every ps counts, analog is really running out of steam. Just try to buy a state-of-the-art S&H. You get it if you buy a 16 bit /200 MHz ADC, too.
There is no such thing as "low and stable offset voltage". There is offset voltage, and that dictates unpleasant architecture decisions because the appearant channel delay varies depending on what state of a QPDM signal you happen to lock to. Or so.
We are about to digitize in L-Band, the downconverter / polyphase filter will perhaps be 8-way. That means 8 DDS-es, 8 sin/cos tables,
8 complex mixers etc, dissipating lots of power, but that power will not shift the phase/delay of some analog low pass.;-) have a good night, Gerhard
I have this particle beam trajectory measurement system where lots of fully digital PLLs are used to follow bunches of protons around a particle accelerator. It spits out the bunch trajectories at an aggregate rate of up to 280M bunch positions per second. All FPGAs. A British firm built it for me. Operators love it. I'm in the process of making a second system for another accelerator.
Jeroen Belleman
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Probably true, but our business is burying the complication so nobody else has to worry about it.
I'm not sure about that as a general statement. I've alway been take with the low power consumption of the Philips/NXP now Xilinx CoolRunner CMOS parts - when you didn't tray and run them too fast - which is why I've got a stick of 15 of them in my cupboard here, waiting for a project to exploit them
Why?
But there's a great deal of manual labour tweaking each example to get it's particular linearity respectable. Physicists have graduate students to do that sort of labour. Engineers designing for production can't afford them.
-- Bill Sloman, Sydney
s e ...Jim Thompson | mens | | et | | | | |
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Buyers get bribed by sales people. Junior engineers get snowed by sales people - it's the latest design so it must be better - and so forth. Sometimes the more modern parts are simply cheaper, and still good enough - soemtimes better on every parameter except the one that matters.
I used to field a lot of that kind of query from purchasing when I was at Cambridge Instruments - I tried to answer them fast so that they wouldn't have any excuse for leaving enegineering out of the loop.
-- Bill Sloman, Sydney
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It passed your sim with slightly different frequencies at each input to create a walking phase shift.
You did need to match the gates. If they were simmed as discrete 7400's then you had to take the 4 on the left from one package.
I know. That's why I was surprised it worked with 8 as quoted:
==========quote========== Newsgroups: alt.binaries.schematics.electronic,sci.electronics.cad,sci.electronics.design,sci.electronics.misc Sent: Monday, August 27, 2001 10:26 PM Subject: Re: Help an Analog Guy with a Digital Problem
|> The internal feedback disabled the pulse too soon. The resulting |> pulse width at the final latch was about 1/2 of what it is with |> feedback from the output (~2.5nS vs 5nS). | |Ok. So was your testing of the last circuit sucessful under full load? |
You bet...you're now in a product...E-Mail for details. =========================
-- Reply in group, but if emailing add one more zero, and remove the last word.
Because driving them in a demodulator loop is a completely needless hassle, and won't do as good a job when you're done. Analogue loops rock. Doing it digitally makes as much sense as emulating an op amp using an ADC, a DAC, and an FPGA, i.e. none.
Not true--read what I wrote above. Inexpensive close-tolerance inductors do just fine.
How are you liking being back in OZ? Run into Phil A. yet?
Cheers
Phil Hobbs
Thanks, Tom! I'll have to try that. Does it have deadband? ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
On a sunny day (Fri, 19 Oct 2012 08:59:28 -0400) it happened Phil Hobbs wrote in :
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mm :-) See my posting in s.e.d today with subject: GPS frequency counter + PLL PIC based
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Why do you think that? The DDS syntheisised sine wave is likely to have a lower jitter than you'd get from most VCOs, and you've got a whole lot better idea of the frequency you are synthesising.
none.
There are occasion when an ADC plus digital signal processing plus a DAC do make sense - as soon as you want a non-linear or - worse - a non-monotonic relationship between input and output. For phase-locked loops this happens quite often - as Floyd M Gardener pointed out, the sort of phase-sensitive detector that gives you the best lock doesn't necessarily get you into lock as fast as you'd like.
The DDS approach comes into its own when you want several sine wave sources at once - for detecting at twice the frequency or both in- phase and in quadrature. The analogue techniques for doing this are no less messy and generally give you a poorer quality sine wave.
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Inexpensive close tolerance varactors don't seem to be as readily available. And the tuning range available is rarely impressive.
Varactors have a roughly hyperbolic capacitance to voltage relationship, so getting the tuning loop critically damped isn't going to be all that easy.
Phil Allison does live in Sydney, but I don't expect to run into him - I did suggest (here) that we get together over a coffee a few years ago but he didn't like the idea.
Oz has been fine so far, but we're not yet entirely out of jet-lag. We've been keeping a low profile. I did apply for two jobs yesterday, but that was more to get my name on the books than in any expectation that I'd get anything. My wife wants to buy a car today, which is going to take a while.
-- Bill Sloman, Nijmegen
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DDSs suck for jitter. Unfiltered, looking at the phase accumulator MSB, they have a full clock of p-p jitter. DAC'd and filtered, into a comparator, it's more complex, but much below the LPF cutoff, you're basically quantized to the DAC resolution. Jitter like 1 part in
20,000 is common for a 16-bit system.The real nuisance in a DDS is the damned lowpass filter.
VCOs can be a lot better, and VCXOs hugely better.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
and won't
Slugman is like the yellow line on the road, he's always in the middle, can't take either side but yet, his lines seem to break left or right at every turning post.
He just can't maintain solid facts or lines.
Jamie
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