I've been reading the basics of the PCI-E interface. Unlike PCI-nonE, which is parallel; PCI-E is serial, with slots/cards having 2^n, for n=0-5, serial "lanes" connecting them.
A card can have less, equal or more lanes than the socket, except for physical space limits. [The socket may be 4 lanes wide; an 8 lane card won't fit. But it could be an 8-lane socket with only 4 implimented.]
The motherboard/card automagically negotiate how many lanes work with a card. Further, newer lanes runs at higher bitrates than older ones, but can fall back for compatability.
Besides flexibility, the serial scheme negates the issue of clock skew; it can handle one lane's data arriving later than others, etc.
Then there's some kind of crosspoint switch that gets the data where you want it. I'm told that SATA data gets similar treatment. I don't know if USB and FireWire also do.
My curiousity is that switch. With a say 6 slot motherboard, 3 slots being 32 wide, and one each 16, 8 and 2.... add in the 4 SATA channels and ???, and you have a LOT of channels into that crosspoint switch. And at the coming 1GB/s rate per lane; that's a lots of bits.
How big are those crosspoint chips, anyhow?