PCB with repetitive design

The way to repeat a portion of a circuit is to build it as a component and "insert" the component several times in the main circuit. Most PCB tools should support this.

d "insert" the component several times in the main circuit. Most PCB tools should support this.

That's fine but I need a 10x10 grid, plus all the nets. The perimeter unit s are slightly different but a demux chain could solve that. How do you co nnect a wide track? Also, there's another variant on the unary selected mu x that takes one more input than selections.

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and "insert" the component several times in the main circuit. Most PCB too ls should support this.

its are slightly different but a demux chain could solve that. How do you connect a wide track? Also, there's another variant on the unary selected mux that takes one more input than selections.

Thanks for everyone's remarks so far. I sketched out the result output I w ant informally with a small text processing tool.

Note the perimeter units are all slightly different due to the effect of th e muxes, even beyond the different axes.

It's not even done and the process is repetitive and error-prone. What too ls are there to do something like this?

It can be done, but first thing is to separate it into layers, with no trace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

I want informally with a small text processing tool.

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f the muxes, even beyond the different axes.

tools are there to do something like this?

ace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

Nice American cinema reference. The rest depends on the exact choice of pa rts. Or should gates be drawn instead of parts? Would you just lay it out with graph paper? Nets can be given width in the diagram by calculating t he bounding rectangles of the lines: half the width times the unit tangents plus both normals at both endpoints. Or should I use demux ICs instead of the group variation? Or can I talk implementation with someone to put it in Gimp?

at tools are there to do something like this?

trace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

parts. Or should gates be drawn instead of parts? Would you just lay it o ut with graph paper? Nets can be given width in the diagram by calculating the bounding rectangles of the lines: half the width times the unit tangen ts plus both normals at both endpoints. Or should I use demux ICs instead of the group variation? Or can I talk implementation with someone to put i t in Gimp?

It's not clear to me what the cells are. There are eight boxes in each cell . Are they separate chips? How big are they? Can the full matrix fit in any reasonable sized PCB?

What tools are there to do something like this?

o trace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

f parts. Or should gates be drawn instead of parts? Would you just lay it out with graph paper? Nets can be given width in the diagram by calculati ng the bounding rectangles of the lines: half the width times the unit tang ents plus both normals at both endpoints. Or should I use demux ICs instea d of the group variation? Or can I talk implementation with someone to put it in Gimp?

ll. Are they separate chips? How big are they? Can the full matrix fit i n any reasonable sized PCB?

How many single-track nets can fit on a board on each axis? In the definit ions I say:

name= "Bits Mux Sel And", part_name= "2x2 And Gate", pos= ( xL+ 60, yT+ 28 )

Etc., but I'm just guessing about the pin names after that. The center rec tangle is the "Bits" chip, which I just say is a "4-Bit MS CDE Latch": mast er-slave, clock data enable. I'll draw the gates separately if I have to, but we're just talking size, not feasibility. Note the two main tracks in each row/column are usually implemented as one with hackery. Other levels of definitions are shown on the project webpage, reposting from 8/13:

What tools are there to do something like this?

no trace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

of parts. Or should gates be drawn instead of parts? Would you just lay it out with graph paper? Nets can be given width in the diagram by calcula ting the bounding rectangles of the lines: half the width times the unit ta ngents plus both normals at both endpoints. Or should I use demux ICs inst ead of the group variation? Or can I talk implementation with someone to p ut it in Gimp?

cell. Are they separate chips? How big are they? Can the full matrix fit in any reasonable sized PCB?

itions I say:

ectangle is the "Bits" chip, which I just say is a "4-Bit MS CDE Latch": ma ster-slave, clock data enable. I'll draw the gates separately if I have to , but we're just talking size, not feasibility. Note the two main tracks i n each row/column are usually implemented as one with hackery. Other level s of definitions are shown on the project webpage, reposting from 8/13:

So, are the cells implemented in single chip? If not, how many chips?

e: [snip]

h cell. Are they separate chips? How big are they? Can the full matrix f it in any reasonable sized PCB?

initions I say:

rectangle is the "Bits" chip, which I just say is a "4-Bit MS CDE Latch": master-slave, clock data enable. I'll draw the gates separately if I have to, but we're just talking size, not feasibility. Note the two main tracks in each row/column are usually implemented as one with hackery. Other lev els of definitions are shown on the project webpage, reposting from 8/13:

e%20transpose.html

The cells have 6 words and 10 flags, plus power clock and ground. So we're looking at 61 pins (8x8) at an 8-bit word for the interior units, or 397 a t 64 (20x20). We might prefer 8-bit since that's the conventional addressa ble unit. Should I be looking at those space optimizations? Multiple chip s would have as many or more total pins. Or would pins not be the limiting factor?

I think trying to do this with standard graphics tools is pointless unless you want to generate your own photos which I think you will find the board fab houses will shy away from using. You need to produce a Gerber file output. The best way to do that (unless you want to learn the Gerber format and write your own tool) is to use a PCB layout package. FreePCB is not a bad one and it has a support group with some folks who can help you do the step and repeat thing you need.

Do you have a machine readable schematic that can be used to generate a netlist?

e: [snip]

trace crossings. DO NOT CROSS THE BEAMS (Ghostbuster).

f parts. Or should gates be drawn instead of parts? Would you just lay it out with graph paper? Nets can be given width in the diagram by calculati ng the bounding rectangles of the lines: half the width times the unit tang ents plus both normals at both endpoints. Or should I use demux ICs instea d of the group variation? Or can I talk implementation with someone to put it in Gimp?

There could be a number of different discrete units, 4 per operation. But the board definition would be different for every combination. In theory, if we're drawing individual gates, it wouldn't be hard to take to silicon.

The rectangles and lines shouldn't be hard to convert to the proprietary fo rmat. How much soldering is practical?

What about that nomenclature for those muxes? I have 15 "parts" defined so far including little old "1x Not". I'm guessing the representation is con ducive to verification, but the test bench isn't currently extensive.

There is Verilog and writing on the webpage, though I haven't ascertained i f it's compliant or compatible. In theory a fab. could read that directly, but routing could be computation-intensive ("NP-Time").

Board fab houses don't do routing. If you want a PCB made you hand the fab house Gerber files, one for each copper layer plus the various solder mask, solder paste stencil and silkscreen layers and a drill file. You also have to give them details on the stackup.

Are you trying to have a PCB made?

But the board definition would be different for every combination. In theo ry, if we're drawing individual gates, it wouldn't be hard to take to silic on.

y format. How much soldering is practical?

d so far including little old "1x Not". I'm guessing the representation is conducive to verification, but the test bench isn't currently extensive.

ed if it's compliant or compatible. In theory a fab. could read that direc tly, but routing could be computation-intensive ("NP-Time").

A PCB is the end result. I'm just struggling to approach it due to all the unknowns. Similar problems have been solved before. I just thought I'd u se the same tools. Maybe we could start by picking out some real parts. T he "worst possible" pinout of a chip wouldn't require much extra routing.

To what extent can you design your own ICs? I'm not exactly ready to pione er the trail of mux names. There are three kinds of selection: plain unary selection; unary selection with an "unselected" input for "no selection" o r "else"; and binary selection, where an "else" isn't coherent. ISTM the n umber of inputs should appear first in the names, and the track width secon d, but the case isn't conclusive.

I can honestly say I have no idea what you are talking about. Sorry.

he unknowns. Similar problems have been solved before. I just thought I'd use the same tools. Maybe we could start by picking out some real parts. The "worst possible" pinout of a chip wouldn't require much extra routing.

If you need more than 1 or 2 chips per cell, your 8x5 sample grid would be impractical. You can't put 100s of chip in a reasonable sized PCB.

Depends on your budget, anything is possible.

FPGAs are very possible.