PCB with repetitive design

A niche for IMS once again?

Best regards, Piotr

Den torsdag den 14. august 2014 07.05.21 UTC+2 skrev snipped-for-privacy@gmail.com:

you could easily find mosfets 10x better than that for that voltage

and what on earth did you use to draw that "PCB" mspaint?

-Lasse

There are two traces across the bottom of the MOSFETs on the top of the board. The placement and layout are restricted by the PCB size constraint. It's already 60mm x 60mm. Perhaps a little bigger, but not much more.

It's just a screen capture of the gerber file view.

Well even if a part has a funny pinout, you can still reroute the nets.

Den torsdag den 14. august 2014 15.52.33 UTC+2 skrev snipped-for-privacy@gmail.com:

what MOSFETs are you using? 6x to220 is more than 60mm and thats with the tabs touching

-Lasse

Top trace:

1. You can extend it out at each end to give a little more heatsinking, and thus ampacity
2. You can extend it upward in 4 places to reduce R of a portion of the track
3. You can add vias to parallel 4 short bits of track on the other (blue) board side, again reducing R and increasing surface area

Lower trace:

1. You can extend it out at each end to give a little more heatsinking, and thus ampacity
2. You can extend it upward in 4 places to reduce R of a portion of the track
3. You can slightly increase the copper area around 2 sides of the 3 pads of its upper section
4. You can spread out a good percentage of its wiggly descent section.
5. You can add vias to parallel 7 short bits of track on the other (blue) board side

There's also of course the option to shift some of the stuff down a fraction to enable fatter tracks up top.

NT

You can also add insulated wire topside or bare wire underside.

NT

#2,4,6 mounted on top and #1,3,5 reverse mounted on bottom of the PCB. Or perhaps just wire them to externally mounted heat sink. We don't really want the MOSFETs adding to the PCB thermo problem.

Den torsdag den 14. august 2014 16.49.37 UTC+2 skrev snipped-for-privacy@gmail.com:

but why all the hassle? it's not a problem routing 3 gate drivers and 6 fets with plenty wide tracks

I'll draw it up later

-Lasse

That was computed for 2 oz copper.

?-)

There are only 4 distinct structures repeated several times. Am I correct in assuming I need a list of parts and coordinates? The repetition is sli ghtly imperfect. Units have unique tests for sequential binary (not unary) addressing.

probably cheap DRAM. Are there any special voltage or current requirement s?

Please use a good CAD tool as Eagle for creating the multilayer PCBs. The exact pin voltages and signal voltage levels can be obtained from the IC datasheets.

It is strange to see a digital circuit handling such huge currents, that are the domain of high-end power supplies. Given the width and thickness of the traces, the power dissipation/waste due to I^2R heating losses will cook the circuit and the ICs in a short time. Please re-check/re-design your circuit. Remember Intel's Itanioum ?

IIRC, about 1A/mm on 2oz. copper, at least for surface traces (internal traces have to be derated from that). On one of my boards, I have 32 5A traces. IIRC, they're 5mm traces.

Sounds like overkill, though perhaps they didn't have enough planes or couldn't afford the surface space for the traces. It's hard to know all of the design constraints just looking at a board. The Idd of the processor I last worked on was ~100A. That was handled on planes though there is no pretending the power system was trivial.

nits, probably cheap DRAM. Are there any special voltage or current requir ements?

opper handle? We need over 10A.

To reiterate, to the end of maintaining a general awareness of the goal, am I correct in that the end result is just like a SVG file for the copper? I couldn't find how to specify repetition in the EDA tool I tried. SVG: sc alable vector graphics. I suppose the "parts" aren't necessarily on the li st. Do you just dip the board in a 1/8" puddle of warm solder at the end?

Most of the IC (MOSFET) can handle over 10A, but we still want to keep the power low.

Here are my 5 top choices:

http://173.224.223.62/motor/fet.php

#3 (FDPN150N10) is the best at 1.5W. However, the input capacitance goes up and switching bandwidth (invert of sum of start/stop/rise/fall time) goes down.

Why are you concerned with what the file looks like? It's called a "Gerber" file, and yes, I believe it is an SVG.

Low end tools likely don't have repletion built-in. If your schematic capture tool has hierarchy, the back end tool likely supports repletion (though the reverse is not true).

I guess I don't understand your questions above.

For through-hole parts this is essentially the process. Rather than being a "puddle" it's a puddle with a fountain or wave in the middle (hence "wave soldering").

Current SMT technology uses a "solder paste" that's spread on the board through a metal mask to leave the goo on the solder pads. Parts are then placed on the goo covered pads. After all of the parts are placed the board is put in essentially an oven and the solder paste melts. When it's all cooled, the parts are left soldered to the board.

It's vector graphics like SVG but scaling it would probably not be useful.

The only one I've used required me to copy and paste to get duplication. if you set the grid step to the repetition interval it's easy to drop the copies in where needed.

There is a way to do that, but I've never tried. also the drill list for the holes is in a different format to the data for the copper.

One method of mass manufacture is called wave soldering and it's a bit like that. The main other method is reflow. Protoypes are often soldered by hand.

Back in the day the technology of making a PCB was not as refined as it is now. Lots of layers were expensive and the bus bars would help prevent boards from warping... at least that was the conventional wisdom. I'm not sure I ever saw a board warp if it came out of manufacturing ok. They even made bus bars that were built with both power and ground giving the distributed capacitance you get with PCBs. This was the days of TTL mostly so that capacitance was not so important I think. TTL responded well to a small cap on each chip.