Hi there,
i?m working on a state machine design with PALASM, but it doesn?t work as intended. Its an excitation circuit for a 5-phase stepper motor driver. Compilation runs without errors or warnings, but simulation shows strange flaws. Any body able and willing to help me?
Frank
Is there any reason not to put the code up here?
I don't trust simulations. For me, they seem to be the source of the funny results more often than mistakes I've made. If it is a smallish project you should be able to check your work by hand. Double check the inverted vs non-inverted because that seems to be the easiest mistake to make.
It might also be worth looking at WinCUPL as an alternative to PALASM. It has been a while since I've done any GAL work but I don't recall too much pain with WinCUPL. If the dialects are as similar as the Atmel link below implies, it may be worth a look just to see how the design behaves in a different environment.
-- Rich Webb Norfolk, VA
"Frank-Stefan Müller" schreef in bericht news:hd0r2q$v7a$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
Did a lot using Palasm at the time and still have a running version 1.5. If you send the source allong with a descryption about what the circuit is supposed to do, I'll have a look at it.
petrus bitbyter
q$v7a$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
as
ge
If
Slightly OT but related. A former customer of mine just called asking me for a copy of the formerly free AMD PAL compiler PLPL V2.3. It's been a decade or more since I have seen this. Anybody know where he could find a copy?
TIA
Bob
Are all outputs synchrous?
yes, they are,here´s the source code:
;PALASM Design Description
;---------------------------------- Declaration Segment ------------ TITLE schritt5 PATTERN REVISION 1 AUTHOR fsm COMPANY mrt DATE 12/10/09
CHIP schritt5 PAL22V10
;---------------------------------- PIN Declarations --------------- PIN 1 CLOCK COMBINATORIAL ; INPUT PIN 2 LI_RE COMBINATORIAL ; INPUT PIN 3 ENA COMBINATORIAL ; INPUT PIN 4 RES COMBINATORIAL ; INPUT PIN 12 GND ; INPUT PIN 13 OE COMBINATORIAL ; INPUT PIN 14 WP1 REGISTERED ; OUTPUT PIN 15 WN1 REGISTERED ; OUTPUT PIN 16 WP2 REGISTERED ; OUTPUT PIN 17 WN2 REGISTERED ; OUTPUT PIN 18 WP3 REGISTERED ; OUTPUT PIN 19 WN3 REGISTERED ; OUTPUT PIN 20 WP4 REGISTERED ; OUTPUT PIN 21 WN4 REGISTERED ; OUTPUT PIN 22 WP5 REGISTERED ; OUTPUT PIN 23 WN5 REGISTERED ; OUTPUT PIN 24 VCC ; INPUT
;----------------------------------- STATE SEGMENT ------ STATE MOORE_MACHINE START_UP := POWER_UP -> S0
;------STATE ASSIGNMENT EQUATIONS -------------------------------- S0 = WP1 * /WN1 * /WP2 * WN2 * WP3 * /WN3 * /WP4 * WN4 * /WP5
;TRANSITION EQUATIONS
--------------------------------------------------------- S0 := LINKS -> S19 + RECHTS -> S1 +-> S0
S1 := LINKS -> S0 + RECHTS -> S2 +-> S1
S2 := LINKS -> S1 + RECHTS -> S3 +-> S2
S3 := LINKS -> S2 + RECHTS -> S4 +-> S3
S4 := LINKS -> S3 + RECHTS -> S5 +-> S4
S5 := LINKS -> S4 + RECHTS -> S6 +-> S5
S6 := LINKS -> S5 + RECHTS -> S7 +-> S6
S7 := LINKS -> S6 + RECHTS -> S8 +-> S7
S8 := LINKS -> S7 + RECHTS -> S9 +-> S8
S9 := LINKS -> S8 + RECHTS -> S10 +-> S9
S10:= LINKS -> S9 + RECHTS -> S11 +-> S10
S11:= LINKS -> S10 + RECHTS -> S12 +-> S11
S12:= LINKS -> S11 + RECHTS -> S13 +-> S12
S13:= LINKS -> S12 + RECHTS -> S14 +-> S13
S14:= LINKS -> S13 + RECHTS -> S15 +-> S14
S15:= LINKS -> S14 + RECHTS -> S16 +-> S15
S16:= LINKS -> S15 + RECHTS -> S17 +-> S16
S17:= LINKS -> S16 + RECHTS -> S18 +-> S17
S18:= LINKS -> S17 + RECHTS -> S19 +-> S18
S19:= LINKS -> S18 + RECHTS -> S0 +-> S19
;OUTPUT EQUATIONS
;WP1.TRST = OE ;WN1.TRST = OE ;WP2.TRST = OE ;WN2.TRST = OE ;WP3.TRST = OE ;WN3.TRST = OE ;WP4.TRST = OE ;WN4.TRST = OE ;WP5.TRST = OE ;WN5.TRST = OE
;CONDITION EQUATIONS
CONDITIONS LINKS = LI_RE * ENA RECHTS = /LI_RE * ENA
SIMULATION
TRACE_ON ENA CLOCK LI_RE WP1 WN1 WP2 WN2 WP3 WN3 WP4 WN4 WP5 WN5 SETF /OE /CLOCK ENA ;SETF WP1 /WN1 /WP2 WN2 WP3 /WN3 /WP4 WN4 /WP5 /WN5 ;SETF /OE CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK
thanx for your help!
;PALASM Design Description
;---------------------------------- Declaration Segment ------------ TITLE schritt5 PATTERN REVISION 1 AUTHOR fsm COMPANY mrt DATE 12/10/09
CHIP schritt5 PAL22V10
;---------------------------------- PIN Declarations --------------- PIN 1 CLOCK COMBINATORIAL ; INPUT PIN 2 LI_RE COMBINATORIAL ; INPUT PIN 3 ENA COMBINATORIAL ; INPUT PIN 4 RES COMBINATORIAL ; INPUT PIN 12 GND ; INPUT PIN 13 OE COMBINATORIAL ; INPUT PIN 14 WP1 REGISTERED ; OUTPUT PIN 15 WN1 REGISTERED ; OUTPUT PIN 16 WP2 REGISTERED ; OUTPUT PIN 17 WN2 REGISTERED ; OUTPUT PIN 18 WP3 REGISTERED ; OUTPUT PIN 19 WN3 REGISTERED ; OUTPUT PIN 20 WP4 REGISTERED ; OUTPUT PIN 21 WN4 REGISTERED ; OUTPUT PIN 22 WP5 REGISTERED ; OUTPUT PIN 23 WN5 REGISTERED ; OUTPUT PIN 24 VCC ; INPUT
;----------------------------------- STATE SEGMENT ------ STATE MOORE_MACHINE START_UP := POWER_UP -> S0
;------STATE ASSIGNMENT EQUATIONS -------------------------------- S0 = WP1 * /WN1 * /WP2 * WN2 * WP3 * /WN3 * /WP4 * WN4 * /WP5
;TRANSITION EQUATIONS
--------------------------------------------------------- S0 := LINKS -> S19 + RECHTS -> S1 +-> S0
S1 := LINKS -> S0 + RECHTS -> S2 +-> S1
S2 := LINKS -> S1 + RECHTS -> S3 +-> S2
S3 := LINKS -> S2 + RECHTS -> S4 +-> S3
S4 := LINKS -> S3 + RECHTS -> S5 +-> S4
S5 := LINKS -> S4 + RECHTS -> S6 +-> S5
S6 := LINKS -> S5 + RECHTS -> S7 +-> S6
S7 := LINKS -> S6 + RECHTS -> S8 +-> S7
S8 := LINKS -> S7 + RECHTS -> S9 +-> S8
S9 := LINKS -> S8 + RECHTS -> S10 +-> S9
S10:= LINKS -> S9 + RECHTS -> S11 +-> S10
S11:= LINKS -> S10 + RECHTS -> S12 +-> S11
S12:= LINKS -> S11 + RECHTS -> S13 +-> S12
S13:= LINKS -> S12 + RECHTS -> S14 +-> S13
S14:= LINKS -> S13 + RECHTS -> S15 +-> S14
S15:= LINKS -> S14 + RECHTS -> S16 +-> S15
S16:= LINKS -> S15 + RECHTS -> S17 +-> S16
S17:= LINKS -> S16 + RECHTS -> S18 +-> S17
S18:= LINKS -> S17 + RECHTS -> S19 +-> S18
S19:= LINKS -> S18 + RECHTS -> S0 +-> S19
;OUTPUT EQUATIONS
;WP1.TRST = OE ;WN1.TRST = OE ;WP2.TRST = OE ;WN2.TRST = OE ;WP3.TRST = OE ;WN3.TRST = OE ;WP4.TRST = OE ;WN4.TRST = OE ;WP5.TRST = OE ;WN5.TRST = OE
;CONDITION EQUATIONS
CONDITIONS LINKS = LI_RE * ENA RECHTS = /LI_RE * ENA
SIMULATION
TRACE_ON ENA CLOCK LI_RE WP1 WN1 WP2 WN2 WP3 WN3 WP4 WN4 WP5 WN5 SETF /OE /CLOCK ENA ;SETF WP1 /WN1 /WP2 WN2 WP3 /WN3 /WP4 WN4 /WP5 /WN5 ;SETF /OE CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK CLOCKF CLOCK
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I looked but couldn't see anything too obvious unless it has to do witht he fact that you didn't latch the direction controls. This could make it mess up on a direction change. This could be an external latch or just part of the design.
Have you tried burning a 22V10 and putting a scope on it?
I assume that WP# and WN# are driving transistors that work the stepper coils. You are using a 9/20 duty cycle on all the coil drives. On each clock, the phase should go 18 degrees.
I haven't looked at the 22V10's datasheet in a while. What is the lowest number of AND gates in the macrocell? Could it be that your compiler has actually not made the correct result without warning you?
=A0 =A0 =A0 =A0 =A0 =A0 COMBINATORIAL ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 COMBINATORIAL ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 =A0 COMBINATORIAL ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 =A0 COMBINATORIAL ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 =A0COMBINATORIAL ; INPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 REGISTERED ; OUTPUT
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0; INPUT
=A0WN4 * /WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
=A0WN4 * =A0WP5
/WN4 * =A0WP5
/WN4 * /WP5
/WN4 * /WP5
/WN4 * /WP5
/WN4 * /WP5
=A0WN4 * /WP5
WP5 =A0/WN5
"Frank-Stefan Müller" schreef in bericht news:hd91fc$skv$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
Did a simple short run but as far as I see the simulation does what it is expect toe do. So what's wrong with it?
PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92) (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992
PALASM SIMULATION SELECTIVE TRACE LISTING
Title : schritt5 Author : fsm Pattern : Company : mrt Revision : 1 Date : 12/10/09
PAL22V10 Page : 1 gc c c c c c c c c c c c c c c c c c c c ENA HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH CLOCK LHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHH LI_RE LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WP1 LLHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHL WN1 LLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLL WP2 LLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLL WN2 LLHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHL WP3 LLHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHL WN3 LLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLL WP4 LLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLL WN4 LLHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHL WP5 LLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WN5 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHL PAL22V10 Page : 2 c c c c c c c c c c c c ENA HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH CLOCK LHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHL LI_RE LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WP1 LLHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WN1 LLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLL WP2 LLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHH WN2 LLHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLL WP3 LLHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLL WN3 LLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHH WP4 LLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHH WN4 LLHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLL WP5 LLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLL WN5 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHH
petrus bitbyter
yes, the display was exactly resembling the simulation result
I suppose this is true, but why? Could the LOWEST number of AND cells be
a concern? I disassembled the Jedec file, of course there are lots of fuses blown, shold mean NOT blown, intact, but it seems to me, that not all AND strings are used, so there should´t be a problem with missing terms.
Frank
I haven't looked at the 22V10's datasheet in a while. What is the lowest number of AND gates in the macrocell? Could it be that your compiler has actually not made the correct result without warning you?
Well, the impossible never happens but I never saw my last PALASM version fail like this.
petrus bitbyter
On Nov 10, 1:15=A0am, Frank-Stefan M=FCller wrote: [....]
erms.
IIRC the 22V10 has the option of inverting the outputs. I was thinking that PALASM may have made OR operations from that.
You also have at least a few ORs in the state change coding.
One flip flop will be set if:
1) It is set and it should remain so OR 2) You are running forwards and it should become set OR 3) You are running backwards and it should become set#1 is likely to explode into a long list of should remain so cases because each case where it is to remain set will be coded using one AND.
"Frank-Stefan Müller" schreef in bericht news:hd91cc$skv$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
Had a closer look at your code and simulation tonight. Apparently you did not want the all zeros at state S0. I know 22V10s have some provision to initialize at power up but I don't remember the correct syntax. I did - and still do - not like it either so I used to circumvent it by defining State 0 to be all zeros (or low or false) which is the "natural" value at power up.
So I changed your code by changing your S0 into S00, making a new S0 which is all zeros and adding a state transistion S0 -> S00. The simulation now looks like:
PALASM4 PLDSIM - MARKET RELEASE 1.5 (7-10-92) (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1992
PALASM SIMULATION SELECTIVE TRACE LISTING
Title : schritt5 Author : fsm Pattern : Company : mrt Revision : 1 Date : 12/10/09
PAL22V10 Page : 1 gc c c c c c c c c c c c c c c c c c c c ENA HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH CLOCK LHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHH LI_RE LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WP1 LLHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHH WN1 LLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLL WP2 LLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLL WN2 LLHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHH WP3 LLHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHH WN3 LLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLL WP4 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLL WN4 LLHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLH WP5 LLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLL WN5 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHH PAL22V10 Page : 2 c c c c c c c c c c c c ENA HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH CLOCK LHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHLHHL LI_RE LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WP1 HHHHHHHHLLLLLLLLLLLLLLLLLLLLLLLLLLLLL WN1 LLLLLLLLLLLHHHHHHHHHHHHHHHHHHHHHHHHHH WP2 LLLLLLLLLLLLLLLLLHHHHHHHHHHHHHHHHHHHH WN2 HHHHHHHHHHHHHHLLLLLLLLLLLLLLLLLLLLLLL WP3 HHHHHHHHHHHHHHHHHHHHLLLLLLLLLLLLLLLLL WN3 LLLLLLLLLLLLLLLLLLLLLLLHHHHHHHHHHHHHH WP4 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLHHHHHHHH WN4 HHHHHHHHHHHHHHHHHHHHHHHHHHLLLLLLLLLLL WP5 LLLLLHHHHHHHHHHHHHHHHHHHHHHHHHHHLLLLL WN5 HHLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLHH
Suppose this to be the behavior you want to see.
petrus bitbyter
"Frank-Stefan Müller" schreef in bericht news:hd91cc$skv$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
Due to the eternal "experimental" phase of the newsserver of my ISP, I cannot see my own postings from time to time. Not the normal way that is. Looking them up in Google Groups makes me see the mess that's made by proportional spacing. So use a fixed font to look at the simulation results.
petrus bitbyter
petrus bitbyter schrieb:
Hi Petrus,
I think you got it!!!!!!!!!! Many thanks to you and all the other folks that tried to help me!
Frank from Karlsruhe / Germany
berichtnews:hd0r2q$v7a$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
work as
driver.
strange
1.5. Ifis
Please note this:
Then try this:
search engines are my friend.
0r2q$v7a$ snipped-for-privacy@news2.rz.uni-karlsruhe.de...
rk as
er.
range
Thanks for the link. I passed it on to my customer. BTW, I did Google before I posted. I just didn't have as much luck with it as you did.
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