Opamps that handle diff Vin > 0 ?

What supply voltage?

What supply voltage?

LMC6482, perhaps, (1.5MHz GBW) about $1.00 ea/100

or maybe

LMP7702 (2.5MHz GBW) about $1.65 ea/100

Best regards, Spehro Pefhany

ode

is

e a

Something's wrong with this question. Opamps have huge gain, and so long as the output isnt hard against a rail, there will not be anywhere near a diode drop of differential input. When you add nfb to bring gain down, this makes teh gain of the whole circuit lower, but does not change the actual ic's gain, which is still extremely high, and the minimal differential input v still remains true.

NT

node

n* is

That statement assumes stability with the outputs out of saturation, and on= ly in some negative-feedback situations does that circumstance hold. Comparator or Schmitt-trigger uses of operational amplifiers are=20 not uncommon, and will misbehave badly if the input doesn't have a suitable differential-input range. The question is a good one (in my opinion, it's a classic!).

is

CMOS inputs can exhibit threshold drift if they spend a lot of time with large differential inputs. Bipolars can have similar problems if you zener a BE junction. For a comparator application, it's usually best to use a comparator.

Cheers

Phil Hobbs

Hmm, is that due to stray ions by any chance?

I recall reading sodium ions trapped in the gate oxide used to cause threshold drift with input flux (i.e., apply a voltage for along time and Vgs(th) apparently changes*). Extremely high purity everything (especially wash water) more-or-less cured that, at least allowing transistors to be used for general purposes.

Presumably, that's quantified as the change in Vgs(th) due to flux being significantly less than the guaranteed variation in threshold voltage by manufacturing and temperature. But if there's still a couple ions remaining, I can see it would still change by a couple milivolts, no? Not important on your power transistor, but a big deal with precision, non-chopper CMOS amps.

Tim

This effect also occurs in digital processes used to implement CMOS ring oscillators or other delay lines consisting of an inverter chain. If the oscillator is stopped somehow, the steady state bias will cause the threshold voltage in every second P-channel fet (the ones with -ve gate bias) to change, and the duty cycle (once the oscillator is gated back on) may go outside of spec.

If the oscillator runs continuously, the effect will be roughly even over all the P fets, and the duty cycle isn't disturbed.

Regards, Allan

is

I thought they pretty much licked that problem. In any case, the OP seems to be happy with mV of Vos, so I doubt even a CA3140 would pose much of a problem.

I assume this application is a bit like a comparator when the input is outside the limits, but acts as an op-amp when the input exceeds the limit, so a comparator would have other issues.

Best regards, Spehro Pefhany