ODB++

ers to

ructure

What about KiCAD?

Perhaps in the next major release?

John ;-#)#

cture

O stands for Owned by Mentor Graphics?

Dubious. This source claims:

Approximately 90% of all PCB designs worldwide are transferred from designe r to fabricator using Gerber RS-274X, and, therefore, regarded by many as t he de facto industry standard.

In contrast, the ODB++ file format is estimated to account for around 10% o f the total PCB market. However, is simplicity and its user friendliness ar e making it an increasingly compelling option.

Best regards, Spehro Pefhany

Seems I mostly see Gerber for fab, ODB++ for assembly data.

Some refer to it as "ASCII", which seems disingenuous and I assume is a historical artifact.

PCB workflows change slowly and aren't very flexible, it seems. I mean, you can very easily parse a pick-and-place file, or CSV or other spreadsheet or table format, but no one in PCBA gets paid to write parsers.

One quirk that comes to mind, a testability report that doesn't detect SMT pads, only vias of adequate size and thru pads. I assign testpoints in my design, but no one reads the outputs, go figure.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

What's this "testability report", generated by what?

The one time I heard about ODB++ was at a contract assembler who wanted to use it to find the pads in the design. There was no reason to consider test points because the boards are tested on a custom test fixture.

We generate both when we release a board. The gerbers are encapsulated inside the ODB structure.

We occasionally write some Python to snoop or edit PCB files. PADS will import and export anything in ASCII, including the parts libraries.

We add BIST multiplexers on most boards, so we can check power supplies and interesting things without fixturing. Sometimes we bring things out on a ribbon cable. Last resort is test points and a pogo fixture, which we seldom do. But I need to do soon for an especially weird little board.

Our test department manager attends our design reviews and discusses testability.

One source sez 80%,another sez 10%. Maybe both are liars. In any case, 100% of PCB fabricators use data supplied to them...

Hmm..guess a single-sided PCB with 50 SMT zeners in series and no vias is untestable by most FAB houses...

Robert Baer wrote in news:Dm5RF.161678$ snipped-for-privacy@fx34.iad:

Place round node pads between them all. Then, once populated, you can probe and test individual or strings of compnents. OR you actually could place a via between each diode pair, and then you would have test nodes all across the bottom of the board. OR you could populate both sides and use vias and two layers to use half the sq in real estate, but twice the profile height.

Prior to population... Fab house... Single layer?

Can be inspected by a computer optically. Not one single continuity test needs to be performed. Hell, human visual inspection would be 100% good enough and likely quicker.

So, yeah, with their bed of nails and such they could test continuity between two nodes, but visual can do the exact same thing just as reliably. In this case. A Single sided board with a single series string of (not yet populated) parts.

You talking contract assembly of the finished product? Then I would NOT test in this case. Better to test each diode first. So if they can do that, then OK. Testing the whole string would require that you construct and provide a test fixture (chamber). (or pay through the nose for them to set one up).

This thing, I think:

Another verification step, though maybe it integrates with flying-probe machines or something, dunno.

Tim

The basic tests don't have any visibility into component type, so they want for example, test access on both sides of series termination resistors. Which would basically double the layout area and negate the value of those resistors, and makes me less inclined to put them in... what a strange incentive.

Tim