Infineon creates chip with 3000 FIN FETS in 65 nm 3D tech.
I've done some designs on a 180nm process... but analog design becomes nasty... the devices are quite leaky :-(
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |
I've seen articles on this variant. The salient channel silicon lets the gate 'talk' to the channel from three sides, which is supposed to reduce leakage (or allow reduced leakage with different doping levels -- I'm not sure which).
So in theory it's a cool way to reduce size while holding the line on leakage. Time will tell if it actually works right or not.
Intel reports their tri-gate MOSFET process, by using a gate that wraps around three of the channel's four sides, reduces 'off' leakage current by a factor of 50 at the 65nm scale.
Cheers, James Arthur
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