Found an interesting perl program that creates fractional dividers in VHDL and Verlog:
So far it seems to be right on, and save s a lot of tinkering. (I am generating precison clocks for something).
I thought that URL looked familiar. Then I remembered that I created it.
It uses a simple search to find rational approximations to a real number. Too small: increment the numerator. Too big: increment the denominator. Stop when the result is within a tolerance band of the desired result.
If I was doing it again, I might use an algorithm based on Euler's GCD. It gets to the result in just a few steps.
Whilst that Perl script should still produce correct results, I changed over to something equivalent to the code in this post some years ago:
Regards, Allan
A generalization of that method is called a Stern-Brocot tree:
It was used by clockmakers to calculate gear ratios. I wrote an implementation in Python a while back for calculating possible transformer winding ratios given a target step up or step down factor:
On a sunny day (03 Nov 2012 01:40:02 GMT) it happened Allan Herriman wrote in :
Allen I have to thank you many times, this code really helped me out. I am brushing up my Verilog atm, and I got some code of my own doing this, but the frequency was not exact enough. Yours was a cut and paste and it worked first time!
I am using a Spartan II, 50 MHz clock multiplied to 200 MHz with the DLL. That gives me 5 ns 'granularity' (is that a word?), 200 MHz fed into your module.
OK, I will have to study that, again many thanks already!
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