Need Dynamic Ram Expert Help

I recently purchased a 1995 vintage piece of test equipment that utilized either 1M or 4M dynamic ram modules (70nS) of the old 30pin SIMM configuration. The embedded processor board that used this ram is based on a Motorola 68020 controller and designed to read and write data to the DRAM using a 16bit wide bus. The board is designed to accommodate two banks of dram. Each bank will consist of two 8 bit simm drams. I?m sure many of you remember this typical motherboard configuration of this era. I am attempting to determine why I cannot get 4M memory to work is this unit(I?ve tried three types). There is a dip switch which you select either 1M or 4M memory, but the ram self test fails miserably when using

4M modules. The 1M modules work just fine. I?ve studied the R/W timing signals (RAS/CAS, etc) as well as refresh timing and all looks to be OK, with lots of margin. What I am not sure of is how to determine the signal integrity, such as overshoot, ringing, etc... One thing that I did was to determine if my power supply was holding up during the R/W process, understanding that there is considerable power requirements for dram during R/W. Using a scope and testing the power supply while triggering off of the R/W lines, I could see no sagging or spikes occurring. I also thought initially that there could be some logic issues when the switch being set to the 4M position. So, what I did was to use some insulating tape to tape up the A10 PCB contact on the 4M simms and pull up the A10 to +5 on the simm to commit this address line. Then set the switch to the 1M position and see if the dram would then work as a 1M part. No luck, still failed the memory test. I could use some help understanding the difference(s) in the dram (other than size). If anyone would like to help out, I would certainly appreciate it as I am quite lost at the moment. Thanks Jim
Reply to
Jim Flanagan
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SNIP

Could it be the refresh counter.? I seem to recall there being 256 and 512 counts as two different standards...

Reply to
TT_Man

I asked him that same question a couple of weeks ago when he posted in comp.arch.embedded, but no answer.

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

The way that I read the datasheets, the refresh rate is 1024 rows within

16mSec or 15uSec each row. This is true for either the 1M memory or the 4M memory. The equipment is running the refresh cycles every 12uSec, so I think that I'm OK, unless I'm missing something.
Reply to
Jim Flanagan

Jim Flanagan Inscribed thus:

Some of that stuff had both 8 & 9 bits! i.e some had parity bits. There was a troublesome arrangement that used three chips of different density. I remember a lot of 286/386 boards that just wouldn't work with the three chip sticks but would with the eight and nine chip ones.

A pity you're not in the UK ! I've hundreds that I keep threatening to throw out. But I just keep putting them back on the shelf.... Maybe next time !

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Best Reagrds:
                        Baron.
Reply to
Baron

I threw out and gave away all mine about five years ago when I cleared out all the

Reply to
terryc

terryc Inscribed thus:

You know you've just convinced me to put the boxes back in the loft ! ;-)

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Best Reagrds:
                        Baron.
Reply to
Baron

Aaah, but it will never turn up unless you throuw them out. {:-).

Reply to
terryc

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