MOSFET gate charge measurement

Hi,

I have a problem where I need to measure the gate charge of an NMOS device which is to be used as the control MOSFET in a buck regulator. What is the simplest way to do this? I did a search in this group but though some answers come close, I cant find the exact method.

Another question regarding the same - Since the MOSFETs are usually driven by a Voltage source + resistor (and not a constant current), what is the utility of the gate charge graph that is usually given on a power MOSFET datasheet. ie. how do you determine the voltage source and resistor values if you are given that the NMOS has to turn on in a given time and you are given the gate charge graph?

Thanks Kais

Reply to
kaisbadami
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check out IRF AN-944

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

Hi Sphero,

Actually I have come across that application note and I tried the setup used therein (in Fig 1). My Vgs rise time and VDS fall times are greater than I expected (I think maybe all the wiring inductance may be causing this - hence I am looking for a simpler method with less wiring!)

I am suspicious of the way that the drain current source is done though. I mean - why not use a pmos current source instead? Using an NMOS current source seems like the VGS of the top mosfet may get overvoltaged a bit when the VDS of the bottom mosfet falls. Also doesnt the 0.1uf capacitor for the vgs of the top mosfet slow down the falling of the bottom mosfet vds in some way?

Thanks Kais

Spehro Pefhany wrote:

Reply to
kaisbadami

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Reply to
tianxin

It's got a constant Vgs isolated supply (from the 9V battery).

Not really, we're assuming the voltage is high enough that the top MOSFET is in the pinchoff region and Vgs is fixed, so Ids is fairly constant. That's the purpose of that transistor and the gate supply circuit-- to make a high voltage constant current source. See figure

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

Hi Sphero

Thanks for taking the time to reply. I will give this measurement another shot tomorrow, maybe reducing the wire lengths to minimize inductance.

One other question, why is it not okay to do this measurement by just connecting the drain to Vdda via a resistor? Wouldnt that be simpler?

Thanks Kais

Spehro Pefhany wrote:

Reply to
kaisbadami

The buck regulator application is in exact agreement with the constant current source load, except in this case the load is in the source circuit. Worst case would be a continuous converter at maximum load current. When the gate is driven through a Vgss + series resistor Rs, the gate voltage builds in the usual exponential way to Vgs(I) where Vgs(I) is the gate-source enhancement voltage required to support the diode+inductor current, the drain is pinned at V+, and the source voltage remains at -Vdiode until this time. Then the source voltage begins to increase causing Vds to collapse, which to the gate drive circuit appears to be a -dVdg/dt, and all of the gate circuit drive current is diverted through Cgd, clamping Vgs at Vgs(I) until Cgd is charged to approximately Vth at which point the MOSFET enters the triode region and Vgs pulls out of clamp to finish its charge-up to Vgss. So the timing is broken down into a delay time and rise time. The delay time is Rs*(Cgs+Cgd)*LN(Vss/Vgs(I)) corresponding to a gate charge of (Cgs+Cgd)*Vgs(I)=Qd and the rise time corresponds to a constant current of (Vss-Vgs(I))/Rs charge up of Cgd to Vss from an initial value of Vgs(I)-V+.

Reply to
Fred Bloggs

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