more lunacy from the BBC

Of course it is, if you actually design stuff. The clbs in an Efinix chip are 4-input LUTs, so you can do any weird 4-input logic function with the same near-zero delay. I tested that on a proto board; adding some logic doesn't noticably affect pin-pin delay. The delay seems to be dominated by io cells.

I just added an extra-cost feature to a pulse generator box, based on the behavior of the 4-input LUTs.

Try digikey for efinix chips. Lots of them.

Yes, there are lots of cheap FPGAs around. Which do you use?

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

By "almost zero" you mean that you can't measure it, and can't be bothered to make any kind of quantitative estimate

Of course you have. An extra-performance feature might induce people to pay the extra cost, if you could quantify the improvement.

But no specific part numbers.

None of them. In the exceedingly unlikely event of my getting a job I'd start looking, but my colleagues would probably tell me what they used. In the bad old day, the software to program the parts cost money, so you tried to use parts that other people had used.

I've certainly quantified it. Pin-pin delays on a T20 vary from about

I wasn't able to see any crosstalk effects.

Here's our test board, a quickie from JLC.

The thing has four delay-and-width outputs. The change allows multiple timing channels to be piped to one output, to do double (or triple or quad) pulses. The added prop delay is zero.

Do you own a web browser? Seems not.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Since I clearly used one to find the "Microchip IGLOO2/SmartFusion2, Microchip ProASIC3(e.g., A3P1000) and AMD/Xilinx Artix-7/Spartan-6 parts"listed below, that's a singularly stupid assertion, even for you. I could have done the same exercise on the efinix range, using the same search string "pin-to-pin delays less than 10nsec" but since the first search didn't pick up the efinix chips, it would have been a waste of time.

You claim to be using efinix chips that do do that well, so why not tell us which ones are that good?

I just named (and you snipped) the T20 and my proto board shows it in plain sight.

We're going to use the T120 in a new design, because it has so much dual-port sram and a nice DDR DRAM interface. We think it may be a bit slower than the T20 as far as logic goes.

If I had an assortment of Efinix chips, I could xray them, and see how many are bond-outs of the same silicon. I'd suspect that bigger chips might have slower pin-pin delays.

That's the bummer about FPGAs: the internals keep getting faster but the i/o cells don't.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

The I/O cells are intentionally slowed down, esp. for rise/fall time.

Some Xilinx families had options for the I/O cells so you could make some of them faster. Making them ALL faster was the sure way to disaster because of ground bounce, esp. when all had the same clock.

I once had a bus fight between a 74AS244 with guaranteed 8*64 mA outputs and a now museum-grade XC3020. The AS244 said 8*LOW and the XC3020 wanted 8 * HIGH. The XC3020 won hands-down, even within valid Voh.

Gerhard

The T20 has selectable drive strength and speed on the pins, or at least on most of them.

Here's the IBIS:

The T20 BGA seems to have no signal crosstalk and no ground bounce. I ran a bunch of stuff (250 MHz DDS, 50 MHz DDG, four 64-bit pseudorandom shift registers) and it was stone quiet. Pulled 24 mA core current.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Not plainly enough for me to have been able to read it. And these posts are supposed to be informative, as opposed to schemes for dispensing clues.

The surface of the board is more extensive and noisier than that the surface of the chip. You need to drive 50R transmission lines to get signals around the board. Some of the clock lines inside package may need some attention too.

If a run several inches long and it's a level only, let it ring a little. Everything will settle an a naosecond.

We have one board we're developing now, where an FPGA drives a trace, then a ribbon cable, then a trace on another board, and finally a CMOS receiver. Total run might be 8", and some signals are edge-sensitive, and picoseconds matter . In that case, we'll keep all the pcb traces

We Spiced all that, and bought a new Rigol fet probe to snoop the first boards.

No big deal, just engineering in the 21st century.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

You don't have a lot of choice if you want to use non-dispersive buried strip-line to move signals around a printed circuit board. Trying to get a higher impedance trace means either a very narrow trace or relatively thick and low dielectric constant layers to sandwich the trace.

The signals covers about 20cm in one nanosecond, so with sub-nanosecond signals you can't go far before the reflection from an unterminated line become embarrassing.

You don't actually want to use CMOS logic levels on that kind of transmission line. ECL deliberately chose a smaller voltage swing to keep the current levels tolerable.

I did specify LVDS signals for the backplane of a fancy timing unit I worked on in the 1990s. It never got built - the academic customer ran out of funding after we'd got the circuit diagrams sorted out, and were running into the dire printed circuit layout tools that the Radboud University had foisted on us. I'd done quite well with software we'd had up to that point, but some Orcad rep had got at the adminstration at just the wrong moment.

Pity. Failures are discouraging.

LVDS makes sense sometimes, but not in this case. It takes twice as many FPGA balls, twice as many ribbon cable wires, and forces the PCB to have more layers (to route out the BGA) which is expensive and makes the dielectrics even thinner.

The 6-layer board with single-ended 75 ohm traces will work fine.

The two outer rows of a 0.8mm BGA can be routed out on layer 1, with 5 mil traces. But every row after that needs microvias and another PCB layer. And each row going in has fewer i/o pins. That's an exponential catastrophe.

Real life poses interesting problems.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Yuck.

Why the insistence ball grid arrays? The T20 is available in 100-pin and

It's elegant to fit all the logic into one package, but if splitting it over a couple of packages makes the routing easier and lets you get away with fewer layers it may be worth thinking about.

And ribbon cables aren't particularly wonderful transmission lines.

You dislike success?

BGAs are small and have near zero lead inductance. And believe it or don't, they solder better.

I can't multiplex fast pulses with picosecond jitters specified.

Our FPGA configuration and runtime data i/o are already a shared SPI interface from the RP2040 CPU.

FPGA-internal routings are small and fast.

The fine-pitch one that we are using is great. I alternate the fast signals with real or effective grounds and get a really clean 75 ohm transmission line.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

They aren't enjoyable, but if you make a habit of pushing the boundaries they do happen, and you can't let them discourage you.

Self-proclaimed success is always somewhat suspect.

Not a lot of help if the points that they get soldered to are hard to connect to anything else. I'd expect the inner areas pf the ball array to be devoted to power supply connections for precisely that reason.

What did you thing I meant by "Only the timing outputs and clocks need to be fast - the data I/O can be multiplexed or even serial"?

As I was saying they would be.

Which isn't much help if the external routings aren't.

That was standard operating practice at Cambridge Instruments in the late 1980s. I was one of the first to use it in production, but one of my colleagues used in a field fix a little earlier.

Ribbon cable terminations weren't designed to cope with sub-nanosecond rise-times, so it wasn't all that great.

That's a pretty horrible 100% overshoot, if brief.

The inductive glitch is from the loop area at the hand-soldered transition from the SMA connector into the ribbon cable. That won't happen on a PCB.

Those $1 chinese edge-launch SMA connectors are not perfect at 20 GHz either, but they are great otherwise, like for 200 ps edges.

The original 3M 50-mil pitch ribbon cable is typically 110 ohms in this gnd-sig-gnd config. 110 can get ugly. I was pleased to find that the 25 mil stuff is close to 75 ohms.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Really? You may be able to make it tidier, and the loop smaller, but doing it right might be difficult.

For your usual definition of "great" which seems to be "barely good enough".

But not pleased enough to find out the exact value. A google search threw up 80R and 83R. You probably have nail down the insulator and it's dielectric constant to get a reliable value.

We do stuff like this all the time, and this case isn't a big deal. Of couse it will work first time.

No, they are great. We did some ATLC e/m simulations to get a good wideband match to the PCB, to get the pads and stackups right. The fat center pin isn't ideal but can be corrected for.

Silly me, I just measured the impedance of the cable that we stock. My old 11802 TDR seems to be pretty good.

Your attitude is that everything that I do is wrong and that you are always smarter. I gently suggest that you reconsider.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

That confession might be held against you. Working right, and working well enough that the customers don't notice anything wrong, are rather different levels of performance.

SMA is supposed to be good to 20GHz. A picture of the connector and and a printout from an electromagnetic field simulation program isn't any kind of evidence of that kind of performace.

"Close to 75 ohms" isn't any kind of exact value.

Everything you do is a bit slap-dash, and if you were a bit smarter you'd be able to make it less obvious. Making stuff that is just good enough to keep your customers happy isn't wrong - it is pretty much commercial wisdom - but boasting about it isn't a great tactic.

A bit of over-design gives you a solution that will last through a couple of generations of up-grades and probably save money in the long term.

As long as we get orders and the checks clear, we are reasonably happy. Personally, I just want to design stuff.

We wanted to design the PCB footprint and stackup to best match that connector. I can share it with anyone who's interested.

My humble appologies for annoying you with things that don't interest you.

E/M simulation isn't slap-dash. I followed that up with a little Dremeling to final-tweak the match.

How is your business doing?

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics