Maximum current for analog switch

Huh.. OK thanks.. can I see this in a jelly bean small signal npn. (3904,4401)* Or was there some mention of low voltage.? In which case it'd be more of a gained up zener (tunneling) rather than an avalanche.

George H.

• I don't have a 'scope faster than 200 MHz, ~ns things are beyond me.

{at high current, with voltage drop in the channel, channel leakage to Vcc is expected]

No, SCR latchup was a lateral surface effect. This is a different problem, the vertical CMOS structure has a parasitic transistor from the channel to the (?substrate or isolation tub). If that voltage drop generates enough emitter current, the transistor leaks (in this case, to Vcc).

Because the parasitic collector is at Vcc, perhaps the tub is N-type, and it's the N channel of the switch that acts as emitter.

Sure!

Note: it's C-E breakdown, tweaked by B-E bias current. The condition which leads to latching avalanche is intermediate between Vceo (base open, so C-B leakage is multiplied by hFE and breakdown is lower and slower) and Vcbo (emitter open, so C-B leakage only).

Some transistors avalanche better than others. PN2369 is classic; 2N3904 is a little slower, but still fast enough for my 350MHz scope.

I've avalanched big honking power transistors too, which are more difficult to do (the range of base bias where large discharges occur is narrow), and somewhat slower (~5ns?), but they fail at pulsed currents not much higher than puny 3904s, presumably because breakdown occurs at a point, and there's nowhere near enough time for charge to diffuse over the whole junction.

Failure manifests as static C-E resistance (10s of kohms), even when fully off. The transistor continues to work as normal, otherwise. Basically it's had a hole lasered through it, causing leakage resistance.

Tim

Note also, about the only other fabrication info present in the datasheet:

The substrate is VCC (which sounds quite unusual to me, but there you go!).

Presumably, one of those tubs gets forward-biased, and it BJTs current straight from the substrate.

Why it was designed to have PN junctions in parallel with channels, I have no freaking clue.

But it would hardly be a lone example of shitty design in the 74HC series. Just look at the 4046...

Tim

Huh, OK I think I saw Dave's video... another circuit to try. Thanks, George H.

And the 7046, and the 9046. All crap in different ways. Using any of their oscillators is an exercise in futility--they're nonlinear by factors of 3:1 to 7:1, and quit entirely when the control voltage goes below about a V_BE. The oscillator in the metal-gate 4046 is pretty linear and tunes a good 100:1, sometimes 1000:1. That's the sort of thing you want an RC VCO for.

The "improved" phase detectors of the 7046 and 9046 aren't worth the huge price premium--you just hang a 1M resistor to ground from the PD2 output, and that pulls you off the dead zone just fine. It's only a few nanoseconds wide.

(I have to ration myself--if I start hating on the HCx046 too often, I'm liable to go on to the 555, and then where would I be?) ;)

Cheers

Phil Hobbs

There are lots of tiny-logic type CMOS gates that will make a pretty nice 600 ps edge.

Eclips Plus logic has typ 130 ps edges. You can buy an EP gate or flop from Digikey.

Some ECL, and some Analog Devices comparators, have 0.8 volt edges in the 40-50 ps range. So it's not a big deal to hack up a little thing that makes good sub-ns edges for testing scopes and things.

Clean steps are more useful than the lopsided glitches one gets from a simple avalanche pulser.

Doesn't seem correct. I haven't seen a N-type substrate since the mid '60's

Head up posterior orifice ?>:-}

...Jim Thompson

Yeah, like the part of my post that was snipped.

On Wednesday, August 17, 2016 at 7:20:20 AM UTC-7, Jim Thompson wrote: ...

...

Supertex designed a high-voltage CMOS ASIC for me in 2001 where I had to connect the substrate to the +170V Vpp rail - presumably that was on an N-type substrate.

At the same time they also did a mixed signal high-voltage companion device where I had to connect the substrate to the most negative voltage.

kevin

Supertex always does strange things ;-) In the mid '60's (at Motorola) we did a hybrid power amplifier made up of two bipolar chips, one with good NPN's (P-substrate) and one with good PNP's (N-substrate).

That's the normal P-type substrate. ...Jim Thompson

I was just organizing some files and came across this.

This is a fast cmos spdt switch that I considered using in an app sort of like yours.

You can clearly see the break-before-make delay, about 2 ns at the end of the positive pulse out. And the charge injection offset in the hi-z load case. Actual switching edges are really fast.

The delay was bad for my app, but might be good for yours.