MAC Architectures

Tim Wescott · 2005-10-19T13:25:12+00:00

Jeorg's question on for an under $2 DSP chip got me to thinking:How are 1-cycle multipliers implemented in silicon? My understanding is that when you go buy a DSP chip a good part of the real estate is taken up by the multiplier, and this is a good part of the reason that DSPs cost so much. I can't see it being a big gawdaful batch of combinatorial logic that has the multiply rippling through 16 32-bit adders, so I assume there's a big table look up involved, but that's as far as my knowledge extends.Yet the reason that you go shell out all the $$ for a DSP chip is to get a 1-cycle MAC that you have to bury in a few (or several) tens of cycles worth of housekeeping code to set up the pointers, counters, modes &c -- so you never get to multiply numbers in one cycle, really.How much less silicon would you use if an n-bit multiplier were implemented as an n-stage pipelined device? If I wanted to implement a 128-tap FIR filter and could live with 160 ticks instead of 140 would the chip be much smaller?Or is the space consumed by the separate data spaces and buses needed to move all the data to and from the MAC? If you pipelined the multiplier _and_ made it a two- or three- cycle MAC (to allow time to shove data around) could you reduce the chip cost much? Would the amount of area savings you get allow you to push the clock up enough to still do audio applications for less money?Obviously any answers will be useless unless somebody wants to run out and start a chip company, but I'm still curious about it.-- Tim WescottWescott Design Services

Oct 19, 2005 27 Replies

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Hal Murray 20 years ago

Seems reasonable to me. Use the DCM clock shifter to get a fraction of a clock cycle. 10ns/256 is 40 ps.

I can't quite understand the fine print well enough to work out a design on the fly. Maybe Peter will take it as a challenge.

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Bevan Weiss 20 years ago

I was referring to custom design, not the use of standard cells or FPGAs. It is certainly obvious that if you can't design your cells from scratch then you're just arranging the cells that you have available. I'm not sure if it can be reduced to swapping wires however, though certainly in FPGAs where the entire logic design is already laid out and the only configuration possible is via routing changes then this is the case.

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Alex Gibson 20 years ago

There is a app note

There are a few fft cores included with ise in logicore

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To use the builtin ones (IP cores) new project then add file , select IP(coregen) then wait for it to load the cores. Then configure as required.

Depends on which chip family you have selected to which cores are available.

Interesting to see that you can get a couple of TI dsps as cores for fpga

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List of xilinx app notes/white papers

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They claim a 2uS 1024 point fft

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Alex

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Rich Grise 20 years ago

[whole bunch really useful Xilinx links snipped :-) ]

Thanks! This is a keeper!

Cheers! Rich

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Kolja Sulimma 20 years ago

What is that supposed to mean? Even if your standard cell library consists of only a NAND-gate in one size there are still many degrees of freeedom in circuit design. For many design problems there are architectures that trade off the number of cells for power or speed. Not so for single cycle multipliers. For any practicle multiplier size the number of 1-bit adders is fixed and there exists a complete set of transformations to automatically reach all possible setups even after placement.

I am sure. RTFP. There is a proof in there.

though certainly in FPGAs where the entire logic design is already laid out and

This does not make the problem any easier. Well, mapping for FPGAs is easier, but that is trivial for multipliers anyway. For placement it does not really matter a lot what the grid is and routing actually gets more difficult when you can only use a fixed set of connections.

Kolja Sulimma

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Bevan Weiss 20 years ago

So you're saying it makes no difference if booth encoding is used, or any form of carry ripple reduction? That it's all just a rearranging of wires? Surely not, using a booth encoder requires different components to a simple ripple counter and so has broken that theory.

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Kolja Sulimma 20 years ago

Bevan Weiss schrieb:

You are right, my definition was not exact enough. What I wrote applies to anything that happens after partial product generation.

Carry ripple reduction does not apply to single cycle multipliers. You need to sum up all carries at the end. Producing a redundant number representation at the output does not count, because now you changed the function computed by the circuit.

Kolja Sulimma

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