LTspice, it's been awhile

The switch is a time domain device. Perhaps it is because of the initial conditions. ac analysis starts with the dc operating point (an initialization). It (ac) doesn't do anything beyond time 0. It is unclear what is inside the ADG1411 model. It probably does not initialize as you are expecting for t=0. If I replace it with an ltspice switch, the 12 dB response occurs.

Version 4 SHEET 1 880 904 WIRE -176 112 -208 112 WIRE -32 112 -176 112 WIRE 160 112 48 112 WIRE 256 112 160 112 WIRE 368 112 256 112 WIRE 416 112 368 112 WIRE 480 112 416 112 WIRE 544 112 480 112 WIRE 656 112 624 112 WIRE 672 112 656 112 WIRE 160 176 160 112 WIRE 256 176 256 112 WIRE 368 176 368 112 WIRE 480 176 480 112 WIRE -208 192 -208 112 WIRE 16 224 -16 224 WIRE 112 224 96 224 WIRE 112 256 112 224 WIRE 368 288 368 256 WIRE 480 288 480 240 WIRE 672 288 672 112 WIRE -16 496 -16 224 WIRE -208 560 -208 272 WIRE -112 560 -208 560 WIRE 160 560 160 240 WIRE 192 560 160 560 WIRE 224 560 192 560 WIRE 256 560 256 256 WIRE 256 560 224 560 WIRE -208 576 -208 560 WIRE -112 624 -208 624 WIRE -208 672 -208 624 WIRE 224 672 224 560 WIRE 336 688 272 688 WIRE 336 736 336 688 WIRE 224 768 224 752 WIRE 272 768 272 736 WIRE 272 768 224 768 WIRE -208 784 -208 752 WIRE 224 784 224 768 WIRE -64 800 -64 736 WIRE 32 800 32 736 WIRE 32 800 16 800 WIRE 64 800 32 800 WIRE 64 832 64 800 WIRE 336 832 336 816 FLAG -208 576 0 FLAG 480 288 0 FLAG 672 288 0 FLAG -208 784 0 FLAG 64 832 0 FLAG 112 256 0 FLAG 368 288 0 FLAG 656 112 Out FLAG 416 112 Filter FLAG -176 112 In FLAG 192 560 -13dBCntl FLAG 224 784 0 FLAG 336 832 0 SYMBOL res 64 96 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 5k SYMBOL res 240 160 R0 SYMATTR InstName R2 SYMATTR Value 417 SYMBOL res 640 96 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 51k SYMBOL cap 464 176 R0 SYMATTR InstName C1 SYMATTR Value 1.5nF SYMBOL cap 144 176 R0 SYMATTR InstName C2 SYMATTR Value 4.7nF SYMBOL Switches\\ADG1411 -16 608 R0 SYMATTR InstName U1 SYMBOL voltage -208 176 R0 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 0 SYMATTR Value2 AC 1 SYMATTR InstName V1 SYMATTR Value SINE(1 1 1000) SYMBOL voltage -208 656 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL voltage 0 224 R270 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 12 SYMBOL voltage 32 800 R90 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value 12 SYMBOL res 352 160 R0 SYMATTR InstName R3 SYMATTR Value 1650 SYMBOL sw 224 768 R180 SYMATTR InstName S1 SYMATTR Value SW_S1 SYMBOL voltage 336 720 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V5 SYMATTR Value 0 TEXT 304 544 Left 2 ;.tran 10m TEXT 304 464 Left 2 !.ac dec 20 1 100k TEXT 160 888 Left 2 !.model SW_S1 SW(Ron=1u Roff=10Meg Vt=0.5 Vh=0)

If you replace the ADG1411 with an ADG1412, the AC and DC analysis both work (with the switch operation reversed). There seems to be something wrong with the ADG1411 model.

--Marc

Thanks. Seems odd, one having a fundamental flaw and the other not when the only difference is the polarity of the digital controls. They also have a third variation (1413) with two controls of one polarity and two the other. Because these parts, and the similar ones made by Maxim and TI are all in short supply, I plan to use a resistor install option to flag the FPGA which of the three are being used. The CM will hate having so many different BoMs, some 8 or 9 variations from this one part selection alone. The other parts with multiple variations will just have to select the part used, without other changes. I find CMs get confused with this stuff very easily, but I guess I can understand that. They just want to build boards, not learn how they work.

Thanks. That makes some sense. But as Marc pointed out, the ADG1412 model works with the AC simulation. I guess I should jump through the hoops and report this. I don't recall how difficult ADI makes it to report bugs. Some companies make you jump through all manner of hoops.

I had posted about this at LTspice groups.io. The first couple of replies complained that I had manual grounds instead of the switches connected. Then someone who was sharp enough to figure that out said that the model was problematic, but could be fixed by adding a FET to the schematic, any FET, no need to be connected to anything. LOL

He had parameterized the simulation and I have done the initial measurements I needed. It would be nice to have the -3 dB measurements made automatically, along with the gains, but manual is good enough I suppose. I'm really only trying to verify my manual calculations.

I've always hated parts of LTspice. The UI is amazingly clumsy if you have not used it in a while. The response to the scroll wheel is not linear. Spin it a bit too fast and the zooms in or out far too much! Virtually every control is the opposite of what is intuitive (where intuitive likely means, I'm used to it because that's what 99% of the other software I use does).

But, it does work... mostly, and it allows me to get the job done, even if it's like shaving with cold water and a rusty blade.

Ok, so now I've added some scripting to automate the -3dB measurements. It works, but I can't figure out how to control the lower cutoff from the upper cutoff. The first parametric run doesn't include the -3 dB cutoff at the low end, so it reports the low pass cutoff at the high frequency end. The other steps measure the low frequency, high pass cutoff. Is there a way to tell it to scan from high to low, instead of low to high? Or can it be given a frequency to start scanning from? I guess I can dig into the bowels of the documentation, but "bowels" is a good term for it. The .meas command is very complex and hard to interpret the documentation. I've been down this road before.

Opps, forgot the script.

.meas AC Filter_max MAX MAG(V(Filter)) .meas AC Filter_3dB PARAM Filter_max/sqrt(2) .meas AC fmax_3dB FIND freq WHEN MAG(V(Filter))=Filter_3dB

The simulation is working pretty well at this point. The circuit is a bit groady, with multiple specs that apply in different configurations. So there's a specific order which has to be followed to design all the details. It's nice to have a simulation to confirm you haven't bollocksed it up.

Now I need to run it by the customer to confirm they are happy with the results. I just hope there's enough room on the board for the added chips. I was able to remove on op amp by simplifying the amp section. The new requirement is for a lower voltage output, so I can eliminate the more complex positive feedback, synthetic impedance circuit. We'll see if the various changes make enough room to get the new stuff on. It's a tiny board.