Looking for SMD level shifters to TTL

søndag den 5. september 2021 kl. 01.33.28 UTC+2 skrev John Robertson:

Vih for TTL is 2.0V that is well within the Voh of 3.3V CMOS

My designer is looking to use something like the MAX3001e, I don't think it plays well with TTL. I did spot TI's CB3T on a message board on Xilinx:

Thanks!

John :-#)#

is the FPGA output or input?

What levels?

So you need both drivers and receivers? If it is TTL drivers, CMOS 3.3V is compatible with that I thought, no? For the receivers I like to use quickswitch type devices. A current design uses 10 wide '240 type devices, SN74CBTD3384CPW. They still seem to be available in spite of the shortage... at the moment. TI has 16,000 in stock. They act to limit the voltage passing through the switch to around 3.3V give or take, I don't recall the details. The prop delay through the switch is lightning fast. Only the enable runs through logic with noticeable delays.

Sounding like a broken record proselytizing these things but a number of the Greenpak SPLCs have dual rails so you can have level-shifted IO of arbitrary configuration, they're pretty cheap in quantity, and the mfgr will program them for you.

And you can put some logic in 'em, too!

I'm glad you do keep mentioning them. I believe they are pretty cheap in quantity, no? You develop your program and they supply them for production already programmed, no? Can they compete with a 10 bit shifter that costs a quarter? What's the propagation delay pin to pin as buffers?

I think the cheapest device with the capability to 10 bit de-serialize (if that's what you mean would be the SLG47503, 30 cents programmed in quantities of 500, 25 cents in quantities of 3000+. I think you would need at least 14 GPIO for 10 outputs plus input, clock, and reset, as they tend to come in even numbers of GPIO.

If you can get away with 12 GPIO somehow the SLG46855 is 25 cent programmed for 500, 20 for 3000+:

There's an example of an 8 bit de-serealizer on page 89 here, but you can use more flops and pins obviously, the datasheet says you can have up to 21 DFFs with that one.

There's a page on calculating propagation delay here:

Input to output delay depends somewhat on the type of IO configured, whether the input is Schmitt trigger and the output is push-pull or open drain, etc..non-Schmitt input to 2x push-pull output delay is listed on the order of 15 ns at 5 volts and in my experience I think that's a conservative estimate.

And if you need 10,000+ looks like they'd likely be amenable to go even lower than that.

Any 74xxCTxx, like 74ACT245 will take 3.3 Volt and output 5 V.

On Sat, 4 Sep 2021 16:33:16 -0700, John Robertson snipped-for-privacy@flippers.com wrote:

Only vaguely related, here's 3.3v CMOS to 3.3v PECL.

Version 4 SHEET 1 880 680 WIRE 592 -176 400 -176 WIRE 400 -144 400 -176 WIRE 592 -96 592 -176 WIRE 400 -32 400 -64 WIRE -80 48 -128 48 WIRE -16 48 -80 48 WIRE 160 48 64 48 WIRE 448 48 256 48 WIRE 592 48 592 -16 WIRE 592 48 528 48 WIRE 672 48 592 48 WIRE 688 48 672 48 WIRE 160 80 128 80 WIRE 288 80 256 80 WIRE 128 112 128 80 WIRE 288 112 288 80 WIRE -128 128 -128 48 WIRE 624 192 400 192 WIRE 688 192 624 192 WIRE 400 224 400 192 WIRE -128 256 -128 208 WIRE 400 336 400 304 FLAG -128 256 0 FLAG 400 -32 0 FLAG 672 48 PECL FLAG -80 48 CMOS FLAG 128 112 0 FLAG 288 112 0 FLAG 400 336 0 FLAG 624 192 PECL_THR SYMBOL voltage -128 112 R0 WINDOW 0 51 68 Left 2 WINDOW 3 16 110 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 3.3 0 0 0 1) SYMBOL res 80 32 R90 WINDOW 0 67 55 VBottom 2 WINDOW 3 69 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL res 608 0 R180 WINDOW 0 65 79 Left 2 WINDOW 3 60 44 Left 2 SYMATTR InstName R3 SYMATTR Value 124 SYMBOL res 544 32 R90 WINDOW 0 65 52 VBottom 2 WINDOW 3 70 52 VTop 2 SYMATTR InstName R2 SYMATTR Value 124 SYMBOL voltage 400 -160 R0 WINDOW 0 -93 38 Left 2 WINDOW 3 -83 74 Left 2 SYMATTR InstName V2 SYMATTR Value 2 SYMBOL tline 208 64 R0 WINDOW 0 4 -82 Bottom 2 WINDOW 3 8 -73 Top 2 SYMATTR InstName T1 SYMATTR Value Td=0.5 Z0=100 SYMBOL voltage 400 208 R0 WINDOW 0 57 41 Left 2 WINDOW 3 48 74 Left 2 SYMATTR InstName V3 SYMATTR Value 1.95 TEXT 168 128 Left 2 ;ribbon TEXT 176 160 Left 2 ;cable TEXT -8 -48 Left 2 !.tran 3 TEXT -152 -144 Left 2 ;3.3 CMOS to 3.3 PECL level shift TEXT -64 -96 Left 2 ;JL Sep 6 2021

We only need a few hundred or so shifters, so your suggestion won't help this time - will keep it in mind though! We are likely going with the

We are also likely using the MAX10 FPGA.

Thanks for your suggestions!

John :-#)#

Looks like you know this GreenPAK stuff - which of their devices would easily compete with 74AC245 in 500 lot pricing? Can one add input protection to the chip and how many non-inverting gates are possible?

This would be for interfacing either with a 1mHz CPU Bus and also I/O with the outside world - TTL levels expected, and interfacing to a MAX10 FPGA...

Do they have a good supply time?

Thanks,

John :-#)#

Are you translating 3.3 up to 5? An AC245 might fry doing that.

Use HCT.

This is for interfacing a MAX10 FPGA to mid-70s TTL.

John :-#)#

Good ole bipolar TTL had a logic threshold near 1.2 volts. It would work fine from a 3.3 volt swing.

I use this for 3.3v to 5v and visaversa. MC74VHC1G50

There is one with compliant TTL inputs. MC74VHC1GT50

I have not used the TTL input version but it may work for you.

Cheers

Yes, that would probably be OK for one direction, but I don't think 3.3 logic likes TTL drive voltages...these buffers are for the 6802 based CPU TTL level bus as well.

TI makes some bidirectional translators that are of interest - trying to keep the costs down, so also seeing what Bitrex can come up with with the GreenPAK devices - one needs some quantity, but $0.25 for an 8 bit (more?) IO is hard to beat - but the learning curve to create the part looks intense.

John :-#)#

Classic TTL output was about 3.5 volts, but a soft pulldown, 5 mA maybe, would reduce that to about +3.

So 1K to ground would be about right.