logic specs

We think that wandering all over the place, a period of deliberate confusion, is a fundamental step in electronic design. I know too many engineers that only use textbook circuits and techniques, and who conceive klunky architectures and jump into implementation without considering alternates. Most engineers are uncomfortable with, even afraid of, uncertainty; they want to lock down a design as soon as possible. And when someone points out a better, faster way to do something that's halfway done, they remain committed to what economists call "sunk costs", throwing good money after bad.

Lots of people do the obvious. We don't care to compete with them.

I enjoy the phase of a project where things are unsettled, confusion aplenty, staggering through the dark corners of the solution space. We have three projects in that state now; great fun.

After the confusion phase, we lock it down and switch to the brutally disciplined implementation mode, and most always get it right first pass.

Not many people can function in both worlds, crazy ideas and disciplined execution. It's almost the definition of schizophrenia.

But we do understand high-speed design. Look at my web site. Pick a nontrivial product and tell us how you would do it.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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John Larkin
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I am beginning to suspect that some SPI slave chips will mess up if fed a perfectly clean, but too fast, clock edge. We've seen that happen a few times. One FPGA needed a cap to ground on its CCLK pin to configure, when everything scoped fine with GHz fet probes.

Anybody else seen unexplained SPI bugs when the master makes fast edges?

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Den tirsdag den 27. marts 2018 kl. 18.04.31 UTC+2 skrev John Larkin:

e time. I recall this was a logical issue where it was hard to know what s tate the SPI port was in at any given time. You never really tracked the p roblem down to a cause, you just got rid of the offending part. So why are you telling us about it in a conversation about signal rise time?

not

g you to talk about the topic at hand rather than continually changing the topic.

issue until it is completed. You seem to want to wander all over the plac e, but I guess that is mostly because you just don't want to discuss a topi c you don't really understand.

heets. You justify that on the fact that clock lines like the CS in SPI de signs needs to branch out which is hard to route as a clock line. I asked about real world situations where you traced a problem to the SPI port rise time making the CS line hard to route. You respond with an unrelated anec dote about an SPI part you couldn't figure out how to use with no indicatio n it had anything to do with rise times.

not? If not, why do you keep replying?

n

t*

ng any conclusion you wish. Nothing else in the paragraph is supported.

issue of rise time, then please don't bother whining about all your unrela ted design failures.

an see why your SPI designs fail to work. Total lack of focus.

supply bounce enough to cause double clocking?

don't remember seeing it

Reply to
Lasse Langwadt Christensen

e time. I recall this was a logical issue where it was hard to know what s tate the SPI port was in at any given time. You never really tracked the p roblem down to a cause, you just got rid of the offending part. So why are you telling us about it in a conversation about signal rise time?

not

g you to talk about the topic at hand rather than continually changing the topic.

issue until it is completed. You seem to want to wander all over the plac e, but I guess that is mostly because you just don't want to discuss a topi c you don't really understand.

John Larkin rarely emerges from that total confusion, though he thinks does rather more often than more objective observers see him as managing it.

It does happen.

This is more frequently known as "not invented here" and John Larkin is a p rime exponent of the approach.

Because it's a rather too competitive market for you.

Ignorance is bliss. If John knew more he'd be less confused, and presumably less happy. If it does take him onluy two weeks to tie off his average new project - as he has claimed he must be able to get confused about quite sm all scale modifications.

Being brutally disciplined for ten days out of fourteen?

Not exactly. It's normally called the development environment. Of course te chnology moves on and I once nailed down a twenty year old speculation when I had a programmable logic into which I could finally cram the slightly od d logic.

Why try do your development work for you, particularly when you are an arch exponent of "not invented here"?

--
Bill Sloman, Sydney
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bill.sloman

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