Logic Function Models That Simulate on Analog Simulators, see...
"LogicFunctions_Basic.lib"
on the Device Models & Subcircuits page of my website.
Basic functionality, output stages to be added.
Experimenting, nothing as complex as the "FauxFET" is required, as I first thought.
In a few more days, I expect to release models that only require entering parameters for TR, TF, TD, ISOURCE, ISINK, CEQUIV to match most off-the-shelf devices. ...Jim Thompson
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| James E.Thompson | mens |
| Analog Innovations | et |
Got a wee bit ahead of myself. As I experimented, I decided that the fundamental elements should include their own delay parameters, rather than there being a global declaration.
Thus FUNC_BUF becomes...
.SUBCKT FUNC_BUF A Y VN PARAMS: TP=10ns V_VDEL N_1 VN 1V G_G2 N_2 VN VALUE {V(A,VN)*10nA} G_G1 N_1 N_2 VALUE {(-V(A,VN)+1)*10nA} C_C1 N_2 VN {20u*TP} E_E1 Y VN VALUE {(1+TANH(2.944K*(V(N_2,VN)-0.5)))/2} RCON_TAG1 N_2 0 1G G_GLC1 N_1 N_2 VALUE {(V(A,VN))*(10uA)*(1+TANH(246.6644*(V(N_1,N_2)-15m)))/2} G_GLC2 N_2 VN VALUE {(-V(A,VN)+1)*(10uA)*(1+TANH(246.6644*(V(N_2,VN)-15m)))/2} .ENDS FUNC_BUF
(Unwrap those two GLC lines.)
Thus (as in real life) gate "innards" are much faster than the I/O pins which are encumbered with capacitive package parasitics and external loads.
So the plan is to now go back and develop the I/O functions with their own separate propagation and transition times specifiable.
Caution, to handle any logic type, I've defined all the _basic_ elements for input and output of 0 => 1V.
The I/O pin functions will provide the logic family matching of levels and timing.
Note that these logic elements will run on most any simulator (including LTspice), since they are ANALOG.
Some older simulators may require changes of the VALUE devices to B-source syntax. ...Jim Thompson
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| James E.Thompson | mens |
| Analog Innovations | et |
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