I've been looking at the "linearization trick" for getting a FET to behave as an approximately linear resistor as described in AoE, 2nd ed., pg. 139-140. I can reproduce the graphs on pg. 141, although I've come to realize that one of the reasons they look so good is because they only took Vds out to half a volt (JFET) and 200mV (MOSFET) -- if you run the circuits through SPICE and let Vds run higher, things aren't nearly as pretty.
In any case, what parameters should I be looking for on a data sheet to suggest whether a given JFET or MOSFET is a good candidate for linearization? I had SPICE run through a handful of different randomly chosen FETs, and some are markedly better than others (the VN13 that AoE uses is among the better MOSFETs... and while I don't have a VCR2N model, I suspect it would be among the better JFETs). For that matter, other than preference and gate current, in general are JFETs going to be better than MOSFETs for this application? I've been getting that impression...
What I'd like to do is to build some electronically controllable RF attenuators good to the HF range (30MHz); non-linearities in the resistance will translate into distortion (the creation of spurs). I was also hoping to be able to pass some 10dBm, which is 1V peak into 50 ohms, so I was thinking I'd be biasing the FETs at around 1.5V or so. Should this be pretty doable?
Thanks in advance for advice.
I'll post a representative plot of a linearized FET over on ABSE...
---Joel Kolstad