Level shifting low speed logic signal

If I were you I'd just use a microcontroller to check the voltage at each cell interconnect point then do some math (subtractions) to determine the voltage of each cell. One PIC that I have used that would be suitable is the PIC18F6520, though it is probably a bit of an overkill unless you can put it to some other use as well. You could have the microcontroller stay in sleep mode and wake up say once every minute or so to do the measurements. The only external components you will need are the two crystals (one for the procedssor and one for the RTC) a few decoupling capacitors and a few resistors to make voltage dividers for the analog inputs. If you use surface mount components it will fit in considerably less than a square inch of board space.

I have considered this, but I see multiple problems with this approach:

1. The input impedance of the PIC is small enough that I would have to use fairly small resistors or buffer the divided signal.
2. The 10b ADC of the pic would reduce my resolution to something like

1. I would want to sample much more frequently than that, as, when they are being used, they will be getting drained quite quickly. Sure, I could design some sort of variable length wakeup system so that it'd check more frequently when being drained - but this is getting complicated.

The Linear chip addresses all three of these concerns.

-Michael

You may want to look at the LTC1540. I think it is lower current.

I'm thinking of pairs of comparitors:

Goes high on fault-----------/\\/\\--- ! Power in ! ! ! series ! !/ e Goes low on fault-----------------! PNP !\\ ! To base of NPN common to all.

That can be problematic for two main reasons: 1) 12x in parallel and any kind of temperature range makes for quite a bit of potential leakage current against which a single LO BATT must be detected, and 2) the requirement to minimize battery current drain for any battery state, especially in LO BATT. Pulsed BATT_LO current output may be better. I don't see anything about transition times in the datasheet, but they can't claim logic compatibility if it's much more than 500ns. View in a fixed-width font such as Courier.

. . . . . ^ . | . | . +----+---------+-[10k]--||----. . | | | 10n | . --- | | | . - | LTC1998| .-------+ . | | | | | . | [ra] |\\|1,5 [1M] | . BATT | CF | 3,4| \\ | |< . STACK +-||-+-------| >-----+-----| 2SB1722J . | opt| | / 6_______ |\\ . | [rb] |/| BATT_LO | . | | 2| | to gnd ref'd . +----+---------' /' current pulse . | / detect . | / . | / . v / . / . / . / Vcc . / | . / [10k] . / | _______ . current / +----> BATT_LO . wire-OR / | . / 100n |/ . +---||---+-------| . | | |>

. | | | . [10K] [100k] | . | | | . | | | . '--------+---------+-- . GND . .

You missed the point about the pairs. There are only 6 transistors but still it is a point to consider.

We could reduce it further by goinf with 3 groups of 4 like this:

Copied then modified:

This way you only get the leakage of 3 instead of 6.

You can't modify the LTC1998 output, it is fixed at /BATT_LO, active low. And although the LTC1540 is nanopower, it may not be suitable for battery monitoring. The battery monitor comparators are designed to maintain low Icc when both inputs are approximately the same, driving it linear.

The LTC1540 has an Icc less than 1uA when the inputs are equal.

The only real problem with it I can see is that it needs a Vcc of about 2V to operate so the circuit wouldn't work if one cell was stone cold dead.