Yes, the usual :-)
I don't know how much gain they have. Sometimes it is only one or two inverter stages in a uC. Three would be good, like in logic chips. With PSoC you could also use the corresponding digital output and (probably, not familiar with it) cascade that with another digital buffer or inverter in order to increase the gain. At least when using parts in a digital block. But I assume three things can hit:
a. Cross currents can reach painful levels because you are essentially operating the first inverter in its linear region much of the time (when the input voltage happens to be close to VCC/2).
b. Threshold jitter and the noise caused by it might be much worse than on the analog blocks. Not just because they'll be physically closer to the ALU, RAM and such, but also because they are not at all optimized and characterized in this respect.
c. Metastable states: If something in there decides to go berserk at a very high frequency when the input is at VCC/2 this could upset other stuff on the die.