LDO specs

Look at page 12, fig. 8. At 1A, Vd

Yup.

It will.

As long as it doesn't oscillate, that is. Personally I do not trust LDOs much.

It means that it's guaranteed not to be below 4.95V out (meaning 99% of

:-)

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Well that's the next thing. That graph sure is weird. Do the hatch lines mean "not here" or 'here"?

That's not how note 2 reads to me... Why would you specify a VI=3DVO+1V when specifying a dropout voltage?

That graph makes little or no sense. The 0,0 point is no cap at all, the 12,12 point is a cap with 12 ohms ESR. It's not clear if the hatched area extrapolates to, say infinite C with infinite ESR, which is again no cap. So no cap is both unstable and stable, whatever tha hatch means.

The only application schematics show polarized caps.

I hate most LDO specs. Most of them go out of their way to avoid a useful discussion of stability.

I'd use another part that addresses stability better.

John

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Never trust figures. They are just bench test data, not electrical specifications.

I am not sure that graph can be trusted, normally it looks like figure 7 here:

With most LDOs, if the ESR gets too low something bad is going to happen, worst case ... *PHUT*.

No idea. To me that datasheet doesn't make a very professional impression.

That is one poorly written datasheet. The 99% figure is probably some fudge factor to compensate for the finite gain of the error amplifier. Generally in a LDO, you don't have a lot of loop gain since stability is more important that a few mV of output voltage accuracy.

The part is a bit cheesy in the GBD department, but perhaps no worse than most stuff on the market. In the dark ages, you just GBD's say a pins capacitance, something where it probably isn't worth the cost to measure in a lot of situations. This part has leakage currents that are GBD'd. The PSRR spec is odd, since you wouldn't expect a part to be typicalls 75db but could be as poor as 45dB.

Having designed a few of this type of chip, I prefer a p-fet pass device over the PNP since as you approach dropout, the PNP will bleed current out of the base.

The nice thing about a p-fet pass device is if the part is designed properly, the high frequency PSRR is determined by the CDG of the pass device and the filter cap. You can get very low feedthrough with good chips. With PNP pass, if you glitch close to dropout, the anti- saturation circuit in the chip comes into play. Figure 11 shows the classic saturation problem as you approach dropout with a bipolar pass device.

If the goal is to get rid of switcher noise, I'd think twice about this part, or at least carefully evaluate it on the bench over temperature for it's high frequency PSRR. This part doesn't even show a PSRR versus frequency graph.

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I know, I've found in the past a lot of LDOs somehow dip a lot in the PSRR near about popular switcher frequencies. That's why I usually add a LC filter before the LDO. But in this case I have height, space and cost constraints for this design. And the ST part is one of the few parts that will (apparently) give 1A output with less than 1V dropout. Lots of "ultra" low LDOs don't give 1A output. What a life. Thanks to all for replies.

Take a look at table 3 before you do that with a DPAK or PPAK. With 6V in and 5V out you'll be burning a watt and that gets really toasty, really fast. Muy caliente.

Maybe I'll make a bumper sticker "L-D-O, no-no-no" :-)

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So what is your alternative to LDOs? Hopefully not roll your own.

I think these MOS LDOs are pretty good. MOS is mushy, but it's a good kind of mush.

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TI has a few MOS-pass LDOs that can handle high current. I don't know the product line off the top of my head, but I've used their LDOs without issue. TI generally runs the PSRR v frequency to a MHz because they know people do put these after switchers. (AKA living in the real world).

Rolling one'w own makes a lot of sense sometimes. For running really sensitive stuff off switching regulators, I like to use two-pole capacitance multipliers with really slow op amp feedback loops wrapped round them. Gets rid of 50-500 kHz to the tune of 100 dB.

Cheers

Phil Hobbs

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Oh I like that, the opamp takes care of the crappy "DC" performance of the cap. multiplier I assume.

George H.

Yes, I have rolled my own. Less grief that way. But my usual alternative is a switcher.

First I'd want to see some guaranteed specs WRT stability. Not some "typical" graph but hard min and max numbers in the columns.

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I have designed several "roll my own" LDOs for specific tasks. Try to find one that can withstand a 35V drop or is stable into large good capacitors and you will see good reasons to do it.

They also often have very poor high frequency line noise rejection or just stick their legs in the air if you let some RF leak onto them.

If you are going to need a reference in the design, it is often a good move to make it bootstrapped by making it work the LDO. It makes the LDO just basically an op-amp.

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I assume it is something like what I did:

Switcher ---[B]-------+--------+--[C]--GND ! ! [R] ! ! ! ! !/e +V1 +------! PNP ! NPN ! !\ Ref---!+\ !/ ! ! >---+--[R] --! ! --!-/ ! !\e ! ! ! ! ! +--[C]---- ----[R]-+--+--Load ! ! +------[R]----------------------- ! [R] ! GND

The bead and capacitor in the switcher path is just to remove the stuff up in the many MHz band.

The emitter resistor on the NPN is a very low value. 5 Ohms seems to work ok. It just keeps the gm of the output section from changing too much over the range of loads. If you use a buried zener reference, you can keep the noise on the supply down around 200nV/sqrt(Hz) so the amplifiers PSRR can easily do the rest.

The worst thing about that config - and I'm doing a couple right now - is the poor transient load regulation. It's great for steady loads. The ideal regulator would clean up a noisy bulk supply to nanovolt levels and still be stiff at the output.

John

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I'm not sure I follow you here. By bootstrapping, I would interpret that by having the voltage reference powered by the LDO output. Totally doable, but you need to watch start up. Bootstrapping the voltage reference is good for getting better low frequency PSRR.

Not easy to explain, but I use a different bootstrap technique. Design the bandgap core so that it doubles as a shunt regulator. Feed the shut regulator with a current source. This helps to isolate the bandgap from the power supply rail.

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Bootstrapping helps the PSRR across the band. If the reference sees a nearly constant supply voltage with very little noise on it, the output is generally as quiet as the technology will allow.

Band gap references are always very noisy things.