Anyone that has deeper knowledge in the DUPline serial protocol? As to my knowledge, 0-level is 8,2 V. 1-level is 2,2V or less Channel-Generator =3D Master-Generator by "inactivity" =3D all bits zero sends out a continuous sync train, 8 ms of 1, followed by N (32, 64, 128) pulses at time interval 1 ms, each pulse 1 for 0,3 ms, 0 for 0,7 ms, to describe the 0-signal.
When 1 is transmitted, this is done by reversing the actual pulse, 1 for 0,7 s, 0 for 0,3 s.
When a device on the bus wants a bit to become 1, it will short the bus (typical voltage is 0,7V). This will be noted by the MG / CG, that answers with a regular 1 sequence.
BUT: How does the MG recognince that someone else wants this bit to become a 1? Is it the lowering in voltage ( from 2,2V to 0,7V), or is it the signal remaining low (like < 4V) during the time of 0,3 - 0,5 ms, ie when the master tries to make a zero?
So, how long must an external device keep low to set the 1?
Best regards, G=F6ran I =C5hling