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isolated delta-sigma converters

78kSPS, ENOB of 14. Yawn. LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by 19 to match the delta-sigma slug would bring you a tad above 2 more bits of processing gain. And you can use the fast bitstream for overcurrent/overvoltage protection purposes. The delta-sigma would be fast enough to report the primary side destruction, if you are lucky. and the SAR is dual/simultaneous sampling, so you can measure current and voltage with the same part. I use exactly this configuration in another project for mains synchronization and I'm planning to use it as well in a bridgeless totem-pole PFC.

John already has an FPGA around there, so the deserialization of the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Reply to
Piotr Wyderski
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Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we could have different lowpass filters in the FPGA for different purposes, trade off resolution for speed as needed.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

That is interesting. It's only 12 bits, and we'd have to gain up and maybe range switch our current shunt voltage. And add some common-mode input voltage to handle our bipolar sine waves.

About a wash.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

What I like about Delta sigma A/Ds is that you only have to have a

-3dB RC filter on the front end instead of a high order sharp filter.

Same thing I believe for the oversampling D/A converters.

Reply to
boB

mandag den 17. juni 2019 kl. 23.04.47 UTC+2 skrev boB:

Delta-sigma basically work the same in both directions

Reply to
Lasse Langwadt Christensen

We use a 20-bit delta-sigma DAC, the DAC1220. It's awesome.

It includes the output filter; all we do is supply two caps.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

No, it is the braindead LTC naming convention. Only IXYS outruns them with their habit to use the output of MD5 for their part names, I believe.

1407 is 12 bit unsigned, 1407-1 is 14 bit unsigned, 1407A is 12 bit but signed and 1407A-1 is signed 14 bit. Go and hit them with something heavy, if you please.

It has a decent internal 2.5V reference and the input stage is differential, so it would be straightforward.

Best regards, Piotr

Reply to
Piotr Wyderski

MAX5719? Best regards, Piotr

Reply to
Piotr Wyderski

20MHz is the bitstream rate, but you need some time for the slug to crawl up. Actually, 256 cycles for a decent resolution. A SAR provides the result in a single shot.

It is exactly the same with any other ADC architecture. The magic of decimation and processing gain.

The high-speed 1.5MSPS SAR output is used for range checking, its decimated by 4 variant feeds a PLL, further decimated by

15 is used for some phasor analytics (@25kSPS and about 17 ENOB).

Best regards, Piotr

Reply to
Piotr Wyderski

mandag den 17. juni 2019 kl. 15.40.05 UTC+2 skrev John Larkin:

don't forget the delay in the lowpass filter needed, it might get tricky when you try to close the loop

Reply to
Lasse Langwadt Christensen

Single shot? An SAR requires a clock for each bit. Did you mean a flash converter? Good luck with a 20bit flash converter. ;-)

Reply to
krw

I meant a single transmission burst, not the slow accumulation process in the reconstruction filter. Send 34 pulses and you have your two

14-bit results sitting in a shift register. You can have up to 1.5e6 such bursts per second in this particular case, which allows for ~700ns response time to an event.

Best regards, Piotr

Reply to
Piotr Wyderski

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