Is This Spice Model Accurate?

Ewww, LEVEL=1...

Is it really worth simulating the thing? I mean, are you just using it as a switch or something? Might as well use a SPICE switch, plus a couple resistors and capacitors to crudely approximate the rise and fall time (if even those are at all important).

Besides the shitty model, there's no [sufficiently nuanced] model of Cgd, or recovery, or package parasitics, or...

If you do, well and truly, need to simulate this thing, to the level of having accurate transient analysis results, keep shopping and find one that is well specified and modeled.

As for VTO, I would think that should be negative in keeping with convention, but maybe it's inverted in PMOS. I haven't looked at the exact definition (SPICE .MODEL definitions are the same for all flavors, so search for your favorite simulator's manual and look it up).

Tim

Thanks for the feedback, but for now I am stuck with this device until I can figure out what it is doing right and wrong.

Actually, I think the Vto really is +1 volt. I simulated just the FET and it seems that the *cutoff* voltage, meaning the voltage where the current starts to increase simulates to +1 volt ballpark. As the gate gets more negative the channel resistance drops which is what a PMOS device should do, right? But the channel resistance never gets out of the Kohm range even with -10 volts on the gate, so something is wrong.

The real problem is the circuit it is used in needs an NMOS FET but this device both simulates and works (according to the LT FAE) on their demo board. This is an LTC3109 low voltage boost switcher simulation which I had posted previously, but no one tried to run. The PMOS FETs were added to shut down the switcher by clamping the control input to ground. In order for the circuit to start up cold, the disable must be a high input and the enable must be a low on the input. The strange part is that the DMP2240 works! This is opposite how a PMOS FET should work so I have to assume this is working correctly because of parasitic effects. To top it off I can't get any MOSFET of either polarity to work when I change the circuit to the auto-polarity mode which is what I need.

I noticed that in the simulation when the control input is clamped to ground by a FET, since the FET still has a finite resistance there is still some voltage on the drain when on. It seems the LTC3109 control input switches when the control input is at 0 volts so the thing will still oscillate. If the FETs are turned off while the AC signal is positive that charge gets trapped on the control node biasing it enough that the small control voltage swing won't trigger the switches! So because of the parasitics the PMOS device works oppositely from what it should.

I can get the circuit to work somewhat with a FDC637AN NMOS FET, but because of the trapped charge issue it won't restart reliably. I suppose in the real world that charge will leak off in a few seconds to let it run. This is a circuit that will be running for minutes and hours to get enough power to run the app so a few seconds of lost power is not a real issue. But I just don't have any confidence this will work reliably.

Does this make any sense? I'm having a hard time finding any sense in it.

Well, I ran the graphs on it in SuperSpice, and no, the model is not correct.

For W/L =1 it should be:

Id = kp * Vgst * Vgst

From inspection, at a Vgs= 5V, its (5V- 1V) for a Vgst=4V, it would be only

What I would say though, is that LTSpice is a real pain if you want to actually get behaviour over worst case process corners. e.g. Vt being 4V or

Kevin Aylward

I just fit a high level chip model (Level=48 or some such BSIM3 or BSIM4) to the discrete data sheet ;-)

LTspice tends to be behavioral, which often doesn't lend itself to corner checking.) ...Jim Thompson

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I'm not trying to do corner checking or anything fancy. I want to use the LTC3109 to power a small receiver. But it is a switcher and the noise it g enerates would likely swamp out the signal to be received. So I want to tu rn it off and run from battery/caps while receiving. I asked the FAE what they suggested and they gave me a circuit that simulates fine and runs on a modified demo board. But it used PMOS FETs which *should* have the wrong polarity for the control so that it would never start up cold (no voltage o n the caps). But for some reason the circuit *works* with the disable high and enable low.

So I am trying to understand what the F...FET is going on with this thing. It is hard to tell the FAE his circuit is goofy when it works. Since they have a demo board working with this mod I would run with it and prototype, but they used two TEGs on the input rather than the one TEG auto-polarity circuit the chip is touted as supporting. When I make that change to the s imulation, the FETs stop working right.

I plotted Vd/Id in spice and get 5 kohms with Vgs = -10 volts. That seem s a bit high for a part that is supposed to be in the milliohm range.

I've tried changing to NMOS FETs since that is what I would expect work the way I need it, but they don't work a lot better in simulation.

Rick

As far as published stuff goes, LTSpice has, essentially, zero support for WC. This makes LTSPice, essentially, useless for serious *simulation* based

Like, every component has to be set up with {expressions} type stuff, so its truly a non starter.

What I find strange is, why doesn't LTSPice have WC support? I had this idea that LTSpice grew out of a tool they used internally for IC design, and then decided to give it way as a marketing gimmick. Many companies developed their own Spice's before the Cadence and Mentor came along. If so, I would have guessed that there would be some sort of Rerun support, say a file where you could list model includes to be used on each auto run. I haven't found any documentation that says this is the case though.

As we noted prior, I don't really use MC, but I did recently add full support for this in SS. Its just a button press. I also added in VBIC support, finally.

Kevin Aylward

I don't do Monte Carlo either... AFAIK it's only useful for discrete designs. ...Jim Thompson

LTSpice has zero support for water closets??? :(

Assuming that's' a genuine ???

WC = Worst Case

No ic company will send a chip to fab without extensive WC simulation.

Kevin Aylward

It is somewhat useful for IC designs - provided someone has gone to the trouble of creating reasonable statistics for the model parameters (which is not trivial since many model parameters are not directly physically meaningful, so they may need to vary model parameters together in a complicated way to achieve a good representation of reality).

It is also important to know if the simulator is varying all of the devices together (to model lot-to-lot variation), or between devices (to model matching between devices on the same die), or both. Of course the statistics will be very different for these different kinds of variation.

What I have used Monte Carlo for is figuring out the approximate standard deviation of offset voltages that one would expect from an op-amp, and identifying which devices are responsible for most of the offset voltage. It has allowed me to figure out whether to increase the size of the input pair, or instead increase the size or overdrive of the devices in a current mirror, etc. Spending a long time or a lot of die area in optimizing the matching in the wrong part of the circuit can thus be avoided.

Using Monte Carlo in automated scripts is handy for checking whether some process/temperature/voltage corner causes some devices to operate in the wrong regime where the susceptibility to mismatch is worse.

In theory you could do all of that with pencil and paper and some mismatch data from the fab, but then again in theory you don't need SPICE at all ever. Having monte carlo does help in quickly being able to be quite confident that you'll achieve the required offset voltage and that you haven't wasted a whole lot of die area or bandwidth or current by grossly oversizing stuff.

Of course like any other aspect of a circuit's performance, the design can still be ruined by crappy layout even if your device sizes are perfectly adequate, but it at least allows you to know that the device dimensions are at least theoretically able to meet the matching requirements. With good layouts, I found that the actual performance in the lab was consistent with simulation.

If you are not lucky in where you work or the fab you use, and you don't have good models, then sure Monte Carlo is probably useless for you.

How do you decide how big to make the input devices of an op-amp, if you know that, for example, you need a 500uV 1-sigma offset? Or how big do you make the resistors if you are making a string DAC and you know that you need say 10-bit INL? How do you decide on the resistor sizes in a bandgap? I have seen nomograms used, but I would be quite scared of missing stuff like e.g. unusually big contributions from the second stage of an op-amp, unless I went around and looked up the nomogram for each device and then did a sensitivity analysis. That sounds like the sort of chore that I would happily leave to a computer.

Chris

LTspice (the public version) is a tool primarily designed to sell LT parts. I suspect there's a professional version within the confines of the LT chip design group.

Attend one of Mikey's seminars and watch _very_ closely, lots of undocumented "features" ;-) ...Jim Thompson

At Ti, TISpice is used, but this is as an engine only, integrated transparently into the Cadence Virtuoso environment. I estimate that this saves them millions per year, even accounting for the dedicated cad staff. Its a really good engine. Excellent convergence.

Kevin Aylward

Many of the semiconductor houses have their own "engine". Intel does... but when I used it some 10-15 years ago, PSpice ran circles around it. I used to go home (8 miles each way), run the schematic on my PSpice, come back to Intel (Chandler) and their simulator would still be churning ;-) ...Jim Thompson

My experience with a certain in-house spice was that it was about as good/fast as spectreRF but lacked one occasionally useful feature. The two simulators were used very differently because SpectreRF was pay-per-instance so we could only have one or two licences each, whereas the in-house tool could be run at no incremental cost, i.e. if we wanted to run 50 copies for a week, no problem, nobody was counting. We could set up batch jobs to run all of our corner simulations in parallel, for example. It also affects what computing hardware you buy - for each of the SpectreRF licences (that cost far more per hour than the hardware), you want one bleeding edge CPU of whatever intel has just released and never mind the price, whereas for the in-house tool, you would buy a lot of machines, whatever CPU gives the most bang for the buck, plus use last year's cast-off SpectreRF machines.

Chris

I routinely run small schematics in SuperSpice that run 10 times faster than Spectre on group servers. Spectre has a lot of overhead.

Kevin Aylward