Ages ago (think 1Kx1 devices), you could see *where* individual cells were PHYSICALLY located on the photomicrograph.
Can you realistically infer the internal geometry from the access interface on newer (e.g., high density SDRAMs)?
Ages ago (think 1Kx1 devices), you could see *where* individual cells were PHYSICALLY located on the photomicrograph.
Can you realistically infer the internal geometry from the access interface on newer (e.g., high density SDRAMs)?
Probably not, aren't they 3d structures now? Cheers
Apparently, it is treated as trade secret as it affects reliability, etc.
I guess I will have to determine this dynamically on a "per unit" basis
If you have direct access to RAM chips it should be relatively easy to determine logical info. Deeper that that looks problematic. IIUC to increase yeld RAM has redundant (spare) rows, non-working rows are disabled and accesses are redirected to spares. So if you need geometry info you need to do this on "per chip" basis as pattern of redirect on different chip will be different.
Question is why do you care? If you care about row hammer, then probably one can not do better than testing various access patterns and looking which ones actually lead to flipped bits. Of course, once you gather enough info it will be easier as different chips of the same type should show similar behaviour (redirection to spares will complicate things, but only modest fraction of rows should be redirected). Also, there should be similarties between different types of chips. But all this looks like a serious job.
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