I had a conversation of A/D converters recently, we speculated on the fastest topology, it must be interleaved sampling.
In principle, one could interleave without limit; go to higher and higher time resolutions, attain proportionately higher sampling rates. What's the limit, in practice, given an unlimited budget?
We must assume a quantization, let's say 6 bits, but you might suggest another.
Am 18.03.23 um 23:18 schrieb RichD:
Keysight has a 100 GHz BW scope with interleaved samplers IIRC.
Gerhard
søndag den 19. marts 2023 kl. 00.04.19 UTC+1 skrev Gerhard Hoffmann:
Keysight UXR-Series, MSRP "only" $1.3mill
I don't know what the actual limits are, but the two issues are jitter on the clock, and the sampling window. We like to think in absolutes, but even the fastest sample and hold has a timing window.
On a sunny day (Sat, 18 Mar 2023 15:18:40 -0700 (PDT)) it happened RichD <r snipped-for-privacy@yahoo.com wrote in snipped-for-privacy@googlegroups.com:
Fasted ones I know about have a bunch of comparators the so called flash ADCs: analog.com/en/technical-articles/understanding-flash-adcs.html
Used for video, have one somewhere.
Since A/D converters are not identical, they might produce slightly different digital values even from a steady analog voltage. Thus you might get at least 1 LSB high square wave from a constant input. Thus adding sufficient dither is critical.
I suspect so, also that's what the fastest oscilloscopes do.
I remeber seeing traces branching and fanning out to 64 or some other crazy number of ADCs
I don't think flash is popular any more. Pipeline residual takes less parts and less power.
I knew a guy who did a flash brute force, with 64 comparators. 6 bits at 50 MHz. It was called the SAD-650 CAMAC module.
On a sunny day (Sun, 19 Mar 2023 09:04:48 -0700) it happened John Larkin snipped-for-privacy@highlandSNIPMEtechnology.com wrote in snipped-for-privacy@4ax.com:
Sure, but did you read the link as pdf? See page 8
8 bits is enough for most things (you can always bias). Else use this to design a faster one (not!):SAY GOODBYE TO CODING: MICROSOFT LAUNCHES POWER PLATFORM COPILOT
I expected it to go that way, bit more and all we need is dummies doing wishes to the AI fairy. 'Be careful what you wish for' comes to mind too.
No more schooling needed? We end up as a brain in a petry dish? Are we redundant?
Job intervoew (providing any jobs are left and not already taken by AI bots): Are you a coder? "Yes, see: 'AI design and build me a <your project>'"
AI: "OK, ready in 10 minutes, please enter 10 dollars..."
Yeah, flash converters sounded great, but because of the spread in the response times (caused partly by the resistor string connected to the other inputs of the comparators), their aperture jitter wasn't too good.
The first and last one I used was a TRW TDC1038, circa 1994. (I picked it mostly for fun--I didn't need anything that fast, but the extra cost didn't matter in a POC proto.)
Cheers
Phil Hobbs
This is solvable by calibration, at the expense of a minor part of the full scale (say twice the worst case error you want to correct). I did something similar to get integral nonlinearity from 2-3% down to below an LSB for a 13 bit convertor ...nearly
30 years ago...(can't be true that time passed, can it).The real issue is the one Rick talked about, sampling window/accuracy and of course clock jitter. And budget... :).
We also used a 20 MSPS 8 bit Flash ADC made by TRW to digitize and average ultrasonic signals @ 6 MHz for measuring the inner hull in nuclear power plants. Scopes were analog then and could not average.
Since we were one of the first customers, we were given an extra ADC in a plastic cube. You could see the resistor ladder to the comparators with the nekkid eye. The chip was the size of a thumbnail.
<It was the nearly 68000-sized black chip with the white TRW-Logo in the right bottom.
I also did the top board that replaced the entire 19" crate in the blurred part some years later, from concept to FPGAs, layout, soldering and software driver, and @ 200 MSPS. The computation loop pipeline was 23 stages deep. The Siemens ECL to 8 lanes parallel CMOS chips were just like made for us. :-)
Gerhard
Go on.
Cheers
Phil Hobbs
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