Discrete BJTs exhibit inverse functional characteristics - some specific devices are designed to enhance them.
Do integrated BJTs have the same behaviour? Particularly interested in low Vce/Vec (below a diode drop) and capacitances that may result.
PSpice models don't seem to account for bilateral operation - you seem to have to add another complete (but lousey) device at the same nodes to model this function. Inelegant, to say the least.
RL
Yes.
Of course they do. What do you think isc, nc, ikr, nr, br, var, etc., refer to?
.model qn npn
+is=2.209e-17 nf=1.000e+00 vaf=3.119e+01 +bf=1.164e+02 isc=1.820e-16 nc=1.500e+00 +ikf=4.345e-02 ikr=1.560e-02 nr=1.000e+00 +ise=9.490e-16 ne=2.500e+00 +br=1.565e+01 var=2.499e+00 +re=5.268e+00 +rc=2.131e+01 +rb=1.772e+02 trb1=1.000e-03 +rbm=3.167e+01 trm1=1.000e-03 +iss=8.038e-15 ns=1.000e+00 +xcjc=2.000e-01 fc=7.500e-01 +eg=1.110e+00 xti=5.835e+00 xtb=1.078e+00 +tf=9.400e-12 xtf=8.000e+00 itf=4.345e-02 +vtf=1.760e+00 ptf=1.500e+01 tr=1.000e-09 +cje=4.700e-14 mje=4.100e-01 vje=9.600e-01 +cjc=4.300e-14 mjc=3.900e-01 vjc=7.500e-01 +cjs=7.000e-14 mjs=3.900e-01 vjs=5.800e-01 +af=1.900e+00 kf=3.300e-11Beware that IC devices have _4_layers_
Some process houses even model that behavior during saturation.
...Jim Thompson
Your source chose to let those parameters default.
My libraries currently show 65 different _houses_, most of which sport at least 2-3 different processes.
If you're trying to design a chip you might consider hiring an expert ;-)
...Jim Thompson
Going to have to look more closely at the documentation. A number of these parameters typically sport zeros.
Operation is expected within a diode drop of one supply rail or another. At present I'm concentrating on the negative rail. Still have no access to process house models. Some progress..eh?
RL
You have to be careful comparing models by amateurs with those from (us) pros ;-)
BF, for instance, is the beta with no emitter or base current crowding... NOT what you might measure at IC=1mA
...Jim Thompson
Odd.....these parameters give apparent gains of about three orders of magnitude higher than would be expected, based on straight BF and BR (+40K and -4K) entries. It also reverses prior to the zero base current crossing.
This compared to three other models.
RL
Do yo uknow any? ;-)
Are you talking about reversing the roles of the emitter and collector? It is an old trick used in "solid state" chopper circuits to get low offset (and why are semiconductor versions "solid state" and *RELAYS* not??). Technically, a transistor is still active even if the collector goes toward zero volts WRT the emitter (standard or reversed condition). It is only when the "other" junction gets forward biased where the conditions are different (both junctions then forward based).
Then contact the process house in consideration and request the models. Always free, usually just requires an NDA.
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at
Bill Clinton also had a Stimulus Package. Her name was Monica.
Takes a while to absorb the info in any plot. Looks like all four are unbelievable nonsense......back to the drawing board.
I'm not trying to design an IC, merely exploring/demonstrating feasibility, through the modeling linear of interface functions that can't be readily breadboarded, due to unavailability of the actual integrated structures.
RL
Well.... there ARE multiple transistors on one substrate...from a super-matched pair by some dinky semi house named National Semi, to 5 on a substrate in a DIP (if i remember correctly).
I think Bill just had the package. The stimulus was Monica's.
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