IC design Guru opinion request

Den tirsdag den 3. juni 2014 01.08.23 UTC+2 skrev David Eather:

I don't know, but everything and then some might affect the frequency

-Lasse

Since the R and C will track, the only randomness source is the jitter in the comparators. Seems to me you would do better with ring oscillators. A ring oscillator has more comparators, hence more jitter.

That said, I don't see this oscillator comparison scheme being a really good source of randomness.

Not, I think, to a cryptographer :-)

The problem with using jitter as a source of randomness, is that it's very hard to persuade yourself that the jitter is anywhere near truly random - that is, that it can't be "pulled" or influenced by other things happening within the chip. Two RC oscillators located near one another, or sharing chip resources (power, ground, substrate, etc.) could easily cross-interact - one oscillator's jitter might be influenced by the other oscillator's period.

The crypto guys who develop on-chip random number generators (e.g. for key generation) tend to go to a lot of effort to make certain that their generators aren't either probe-able, or pull-able.

For casual uses, an on-chip RC may well be adequate... but my guess is that it won't satisfy either a cryptographer or a statistician as "random".

Absolutely correct. It's not as simple as people here pretend.

Interesting paper to read regarding the potential flaws in ring oscillators:

Regards, Allan

Except nobody has the budget to build chips with and without all these isolation structures. Maybe they work, and maybe they weren't needed. But that is the analog biz.

It is surprising how much superstition there is in chip design. Nobody wants to be the first to try something different if it isn't essential to do it, just in case it becomes the cause of an all layer revision. The exception is where there is a bunch of empty space on a multi project wafer being put together in-house. Really useful experiments can then be done, as long as the company has the foresight to allocate some layout time to the experiments.

I have seen a few real coupling problems occur, and I may even be able to remember which change fixed some of them. Yes some of the isolation techniques do work, but of course only against the particular coupling mechnanism that they address.

One of the most effective ways to find RF coupling is to watch the offending coupled signal on the spectrum analyser with an open chip running on the probe station. Then cut off non-essential tracks, or alleged shielding structures, etc. one at a time with the laser, until either the coupling changes or the chip stops working. At every stage keep detailed notes, because you don't want to forget and have to start again with a new opened chip. It helps to think beforehand about the order of cuts in order to keep the chip alive as long as possible whilst being able to cut off as many parts as possible one at a time. Perhaps this would make good training for would-be torturers...

The laser pulse can cause latchup (sometimes obvious and sometimes subtle) and this can change the behaviour, so you monitor the supply current for unexpected increases when you fire the laser, and it is a good idea to power-cycle the chip after each laser cut to verify that the measurement wasn't affected by latchup. Sometimes this is impossible, e.g. if you have to cut off a bunch of digital lines that are needed to configure the chip at startup. Usually I'd save those cuts till near the end.

Usually these experiments allow you to at least narrow down the possible coupling mechanisms, and thereby choose a more likely remedy.

Chris

Some schemes have obvious science behind them. For instance, you can run metal signal lines over poly, with poly tied to an AC ground. This is done to stop channel formation when the metal line has a voltage on it above what a field implant can contain. But it also does stop coupling to the substrate.

The moats can be parasitic collectors to improve latch-up, so they aren't wasted, except for the fact that they are probably in a place in the chip not really likely to be involved with latch-up.

Intel has done much research on analog design that will probably never see the light of day in any formal manner.