I am planning to use a bunch of 74HC595's latches to drive some LED displays. I anticipate the supply voltage to vary (intentionally at a slow 1mS rep rate) between 2.5 and 5v with slew rates about 1v/uS. Can these latches still hold their state without changing at these kind of rates? How could I simulate this to get an idea of how much supply voltage swing that could be tolerated before data gets corrupted? thanks, al
Well, this spec says 2V min:
Keep in mind that they need good bypass caps and you'll have to muscle those around.
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I'm going to guess that as long as all the signals to the chip swing in synchrony with the VCC line you'll be OK. I _think_ the problem would occur if you had a chip whose VCC line was going up while another's was going down, or visa-versa.
This could happen within the chip, too, but unless you're using 4000 series logic 1us is a lot longer than the chip can switch, so it'll probably adjust quick enough.
But I'm just guessing. I wouldn't try simulating this, or at least I wouldn't just simulate it -- I'd hook your VCC up to a signal generator and crank up the frequency until you see odd behavior.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" gives you just what it says. See details at http://www.wescottdesign.com/actfes/actfes.html
Why on earth are you slewing the supply voltage?
JF
I'm using it to control the If / brightness of the LED's . Only 1 LED per latch string will ever be lit. I can save space by minimizing #resistors vs simple control circuit without using insanely small parts. When the LED's are off, the supply is 5v , LED's on and supply is about 2.5v to 4v +/- some ripple depending on LED color.
I understand Tim's comment about input levels following Vdd and am also aware that latch power up state depends on device characteristics and mismatch. I'm concerned that mismatch will throw a curveball when there is data in the latch.
al
This sounds pretty nutso to me. Capacitive loading on the output pins could lead to latch-up should they be higher than the power supply.
In theory, for a static cmos circuit, you only need the largest Vt to retain a logic level. I'd prefer you pwm the led itself instead. Better yet, use the max7219.
What's capacitive on the outputs here?
Philips/NXP makes a nice PWM mux chip for LEDs. PCF-something.
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a
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It's not likely to have capacitance across the LEDS, but given how ill conceived this project seems, I figured I'd point out the perils of slewing the power supply when other pins may lag the supply voltage. I have no idea if 74HC chips use epi, but given the cost, I doubt it.
Factory latch-up testing does not move a hard supply. You don't know how many problems have been caused by systems designers that refuse to use shutdown pins because the datasheet might say a few uA is consumed, so they use a pass device on the power pin.
You'd probably consider many of my circuits ill conceived :-)
Sometimes when every penny counts you've got no other choice. I've seen one design where they supplied a uC from mains via a resistor. The rectifier was a substrate diode. Now I wouldn't go quite that far but it sure was clever.
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