High Side Driver

Jan 07, 2014 109 Replies

Yes, obviously. I wasn't trying to solve your problem.

Here's what I'd consider for your situation:

+3v3 -+- | |_ _)| L1 _)| _)| | | V D1 +12v --- -+- | | | ||--' | ||

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

Where do you get one with dissimilar Vz?

Tim

Seven Transistor Labs Electrical Engineering Consultation Website: http://seventransistorlabs.com

You don't, but a dual 20 volt zener would work.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation

Won't isn't the same as can't.

He won't because he can't.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation

Due to Miller, the actual value is Vdd-dependent (in addition to device-dependent). It's easier to overfill L1 and clamp off whatever you don't need. Fewer headaches.

Cheers, James Arthur

Question: Does total Qg include Miller effect?

Yes, and that's why it's Vdd-dependent.

Best regards, Spehro Pefhany

"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com

Spehro -

The graph I looked at for an example showed two Vdd lines so close together that I would have trouble distinguishing the difference on the graph. Never-the-less, I have been warned.

Many thanks.

Cheers, John S

Ain't no Miller in a follower (high-side) configuration. ...Jim Thompson

| James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

Huh! VDD-dependency is due to depletion layer spread. Ain't no "Miller" in a follower (high-side driver) configuration. ...Jim Thompson

| James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.

Sorry, I thought we were talking about common source switching.. mixing two different conversations, I'm afraid.

Best regards, Spehro Pefhany

"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com

P.S. Here's a decent application note on MOSFET gate charge:-

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Best regards, Spehro Pefhany

-- "it's the network..." "The Journey is the reward" snipped-for-privacy@interlog.com Info for manufacturers:

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Embedded software/hardware/analog Info for designers:
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Thanks! That's a good app-note! ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

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| 1962 | I love to cook with wine. Sometimes I even put it in the food.

"Miller" is just a word. There's certainly charge from Cdg in a follower. Lots of charge if Vd is high.

The fet doesn't know it's in a follower circuit. All it sees is the voltages on its three leads.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation

There's no gate current caused by the voltage changing across Cdg?

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation

Sure there is, Cdg, the Miller capacitance, right? That's what I call it, anyhow.

As the FET turns on, dv/dt across Cdg saps off the charge you're trying to force into the gate, by an amount that varies with Vdg(t0).

Depending on the FET (and since you are depending on the FET's particular characteristics), it could matter.

Cheers, James Arthur

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