Headphone amp simulation

As noted elsewhere, I have yet to be able to get PSpice Schematics to install. I used it 15 years ago, and I thought it was very good for PCB based Analog design, which is what I did then. I don't believe that it has the hooks that pro ic design tools have.

For example, a "Fully Integrated" system like Cadence has Schematics and Layout all "integrated". Layout to Schematic verification (LVS) is pretty much a button press. x-probing layout to schematic is button presses. Parasitic extraction to schematic simulation with those parasitics is button presses. Schematic/Layout design reviews are significantly harder with a hodge podge of disparate tools and much more likely to result in errors. Its key to be able to do top level simulations and know that the schematic being simulated is exactly the same one as in layout. 1 wire off in millions will fail the chip and cost a huge bunch of green ones. No one in their right mind would design a uP with layout and design in two different data bases.

I just don't see it as debatable that tools such as PSpice with mix and match layout tools is viable for general, professional mainstream IC design, and that is why, by and large, no one does it. They spend the money on Cadence and Mentor, because it is truly what is actually needed when a mask

There are to many other issues to enumerate, but one other example, PSpice does not have Periodic Steady State Phase Noise. This makes it, essentially, impossible to reliably, 1st time pass, design any system where phase noise matters.

Kevin Aylward B.Sc.

- SuperSpice

Indeed, at that level its all Linux/Unix.

I do use SuperSpice on Windows as a complement to the main work though.

Kevin Aylward B.Sc.

- SuperSpice

Version control databases are available on Windows, too. CVS, for example, is available on many platforms, as is Agile.

Main Bias Generator:

I'm guessing that VREF is around 1.25V, giving 100ua in your master bias generator outputs. That seems rather high. Not a low power product I gather?

1ua is usually the norm.

I like to draw the bias generator transistors in Cadence parallel device ref designator notation of e.g. M1 with a buss output ibias. It makes it easier to add and subtract sources as the design progresses by changing 1 number instead re-drawing.

It looks like all transistors are connected as isolated devices with source to their backgates. For diff pairs I would do that, but for the bias cascodes, I would typically use non isolated to save space.

Off hand, the start-up current turn off (Q1 diode) looks a tad interesting. Relies on having a large double Vgs on the cascode bias transistors so that VBIAS > VCC - Vbe. So, VBIAS wants to be high to ensure turn off, but this limits the output voltage operation range of the current sources.

Oh...its VDD not VCC. This shows your bipolar disorder age...

Kevin Aylward B.Sc.

- SuperSpice

I'm sure it matters a lot in automotive and industrial control systems

LVS is what everyone _not_ in the know throws out there as the reason you need Cadence. Baloney! I can effortlessly and error-free generate any netlist syntax known to man... get an _old_ copy of PSpice (before the ruination of OrCAD and Cadence) and look up "templates".

If I couldn't, how did this...

get laid out, masks made, processed, packaged, and come up working first pass ?>:-}

And one I can't yet show (NDA hasn't expired), summer of 2011, I had an on-site gig in Huntington, Long Island (where I sipped a few with Martin Riddle :-). Carried my little Lenovo laptop with me. Customer had the full Cadence toolset. I quickly showed that I could run circles around the Cadence stuff using my laptop, so I designed all the analog portions of the chip (Mark Tse did the digital... another analog contractor on the team bailed because he couldn't keep up... besides he was of the "every function requires an OpAmp" crowd :-) A junior engineer (older than me :-) was assigned to transfer it to Cadence for documentation purposes, but layout was done using my LVS netlists. Worked first pass! ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Depends on the application and the resistor types available. A trade-off between resistor area and current consumption.

Accuracy was the driving force here. (VGA)

Shows your ignorance, VCC is for analog, VDD for digital.

You're becoming a horse's ass approaching Larkin-level. What's your problem? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I don't know what the world is going to do with out you Jim? guess we'll have to go back to morse code and dry cell batteries to communicate! At least all you need there is some wire wrapped around a thread bobbin held in place via a nail with the spring hammer hanging on top.

Jamie

I am not claiming that its absolutely impossible to do without a full integrated system in all cases, I am saying that it is much, much harder, such that it is not really a realistic option for mainstream professional design. Its pretty much a non debateable fact that designing a modern uP would without the appropriate tools would be impossible. PSpice and micky mouse layout tools just wont cut it there.

So, you were not doing 10 GHz with parasitic extraction then.

Kevin Aylward B.Sc.

- SuperSpice

Oh... ?

VCC - Voltage Collector Collector, VDD Voltage Drain Drain, VEE Emitter Emitter, VSS Voltage Source Source

older guys = bipolar design = VCC/VEE younger guys = mos design = VDD/VSS

I have never heard of any reference to VDD as a digital designator. When was TTL ever VDD ?

Kevin Aylward B.Sc.

- SuperSpice

That Long Island design was for a clutch controller for heavy trucks... carefully controlled application and release... no jerky starts and wear minimized ;-) The whole world doesn't revolve around

10GHz uP's... there are lots of tasks that don't take that kind of speed. However I have done a WiFi repeater at ~5.5GHz with PSpice.

And occasionally I back annotate with extracted parasitics to verify speed. It's not exactly rocket science... and it doesn't take Cadense tools to do it. (Misspelling purposefully :-)

You _are_ aware that an LVS tool can be used to verify that two _schematics_ have exactly the same content (say my PSpice schematic versus a Virtuoso rendition)? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

In MODERN day usage, VDD is usually digital, VCC usually analog... although there's less and less standardization... on cells I tend to use VP and VN. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

I can't agree on that. I have never seen that as an informal standard. Typically I see things like vdd_ana and vdd_dig, vreg, vunreg, etc. Most modern analog design is defacto in pure cmos, say, 95%+ of it, and VDD *is* the norm there. Its pretty much impossible today to even find designers that that know bipolar at all, i.e. gm=40.IC

Kevin Aylward B.Sc.

- SuperSpice

I don't see this is a comparison of Cadence tools against Junior level tools, I see it as a comparison between experienced, expert professionals, with Junior Competency level engineers.

Kevin Aylward B.Sc. snipped-for-privacy@kevinaylward.co.uk

Some of us esoteric types build wonderful performance from BiCMOS... like my...

(Pretty hard to do really good VGA's in pure CMOS)

I agree with that. I cut my teeth on bipolar... it was probably close to 20 years into my career before I did a CMOS design... my first CAD-based as well.

However I could just as easily design with tubes (valves for you UK types :), though I've not had a commercial application.

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

On 31/05/14 19:48, Jim Thompson wrote: [...]

Haha! That reminds me of a citation I picked up some years ago:

"A slower system like cruise control can typically be handled by a mid-level processor such as a 700MHz x86 ..."

-- Shawn Liu of National Instruments in "Embedded Design", November 2002

Jeroen Belleman

I quite assure you that I can enter schematics faster in PSpice (MicroSim) Schematics than you can in Virtuoso... those pull-down menus are a time waster. Plus... in many instances, PSpice simulates faster... particularly on the typical network _workgroup_ crap.

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

We did have a clock... 5MHz... divided down to 156kHz for the sampling (flipping a magnetic sensor and synchronous demod... modeling mentioned in prior posts ;-) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Its the whole environment. Cadence is really quick to work with symbols and schematics and building up a hierarchically design, with modified versions of schematics. I have yet to see any capture program that beats the auto rout wiring/rubberbanding of Cadence. Its totally rectangular from any point to any point.

There are issues with simulation on smaller circuits. I have even been running SuperSpice 20 times faster on some circuits.

For bigger sims, and running the latest APS with multicore support Spectre can run very fast. However, Berkley Design Automation has a plug into Cadence environment FastSpice that screams 10+ times faster still. A point here is that everyone targets the Cadence environment.

Kevin Aylward B.Sc.

- SuperSpice

I am a guitar player, I know all about tubes. I was getting electrocuted when I was 14.

Take up guitar then.

Kevin Aylward B.Sc.

- SuperSpice