GreenPAK Developer mini-review

As far as I can tell they don't even provide a basic test-project to load to check the in-circuit emulation mode and make sure the evaluation board is accepting and passing signal the way it should.

The documentation in the Silego-labeled user guides of the 2016 varaint is pretty good; the main software hasn't changed much but the emulation component is totally different, been re-written since the acquisition, and the later Dialog-branded text reads like:

"Now user can use all Debugging chip control: Emulation/Test mode/Read/Program for external chip

Attention! Ext. VDD (Va) expansion should no be enabled if exist voltage on external VDD port. It automatically disconnects while starting Emulation/Test modew operations for chip with existing external voltage with warning message."

so we know what happened.

Documentation can be done by the third world if they have sufficient suppor t from native speakers who also understand the product. Let's face it, oft en the problem with docs is not really the language they were originally wr itten in, it's how well the writer can write. I know my tech writing is no t as good as a good writer would do. I think it takes some training to mak e a writer understand methods and goals. Not entirely unlike teaching. No t many are natural teachers.

Glad you are making progress. I looked at their chips as hard as I needed to realize it just wasn't a good fit to this design. The design uses a cur rent regulator that is only a diode, a cap, two transistors and a few resis tors. Works well to charge a supercap. A pair of comparators and some log ic to provide a mute function for the sounder. I decided I didn't want to just turn on a sounder, so added a chip to provide pulsing, four shorts and a pause repeated every N seconds.

The trouble I had was making the mute function a reliable thing without add ing logic. It really needs three states, so two FF and some gates, but eve ntually I found a way to do it with the one FF and inverters with an RC to delay the clock from the release of the reset.

So in theory this could all go in the Greenpak since they have comparators, logic (enough to do it "right") and even a pass transistor. But the PFET seems to be on or off. I didn't see any way to control it and no op-amps, so I guess that's not the intent. It would have still required a diode to prevent the supercap from powering the power rail when down. I looked at t he chips with regulators w/ current limits, but just didn't work well. I a lso was not sure it would work at all in this job since it would need to be powered by both sources depending on which was up and which was down. Clo se, but no cigar.

I guess I could have it do the rest of the design other than the current li miter. That would be 4 ICs and seven or so passives replaced. Not sure it 's worth it. Part of the requirements is to be able to locally source all components. I'm not sure that is possible for electronics just anywhere. I've tried to use parts that are available from both Mouser and Digikey and more than one manufacturer. I think the Greenpak stuff is just not very u niversal yet.

It is interesting hearing about it first hand.

Nope, no all-analog parts like discrete FETs or op-amps on board any of them AFAIK. It's "mixed signal" but in a loose sense of the term you get analog compators that feed into the matrix, and DACs and ADCs on some.

IF it works out well enough for this project of mine i'll be gladl it's too fast for a reasonably-priced uP and too much logic to do sensible with MSI chips off the shelf. And I don't know Verilog or VHDL.

I don't think I'd use it for anything life-critical (if I even wanted to do such a thing) there's a ton of errata and unknown-unknowns about this thing, at least to me.

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pport from native speakers who also understand the product. Let's face it, often the problem with docs is not really the language they were originall y written in, it's how well the writer can write. I know my tech writing i s not as good as a good writer would do. I think it takes some training to make a writer understand methods and goals. Not entirely unlike teaching. Not many are natural teachers.

ded to realize it just wasn't a good fit to this design. The design uses a current regulator that is only a diode, a cap, two transistors and a few r esistors. Works well to charge a supercap. A pair of comparators and some logic to provide a mute function for the sounder. I decided I didn't want to just turn on a sounder, so added a chip to provide pulsing, four shorts and a pause repeated every N seconds.

adding logic. It really needs three states, so two FF and some gates, but eventually I found a way to do it with the one FF and inverters with an RC to delay the clock from the release of the reset.

ors, logic (enough to do it "right") and even a pass transistor. But the P FET seems to be on or off. I didn't see any way to control it and no op-am ps, so I guess that's not the intent. It would have still required a diode to prevent the supercap from powering the power rail when down. I looked at the chips with regulators w/ current limits, but just didn't work well. I also was not sure it would work at all in this job since it would need t o be powered by both sources depending on which was up and which was down. Close, but no cigar.

t limiter. That would be 4 ICs and seven or so passives replaced. Not sur e it's worth it. Part of the requirements is to be able to locally source all components. I'm not sure that is possible for electronics just anywher e. I've tried to use parts that are available from both Mouser and Digikey and more than one manufacturer. I think the Greenpak stuff is just not ve ry universal yet.

If you can squeeze it into a Greenpak you can't beat the price. But any ti me you need something more I'm your man with FPGAs. Lattice has a wide sel ection of smaller parts in smaller packages, some non-BGA. I don't know Ve rilog well, but VHDL is not hard. People complain about the strong typing, but they are wussies and expect tools to read their minds. Then when the tool makes a mistake, the blame it on the tool! With VHDL the tool won't t hink for you. You have to tell it what you want. Mostly that means using a data type that suits your needs. Not hard, but it takes a couple of days to get the hang of it. I'm happy to help you want to make the plunge.

Yeah the applications the GreenPAK seems ideal for are glue-logic-like tasks for gap-bridging between analog and digital realm, where nothing exactly fits your bill off-the-shelf where it would be possible but annoying and more costly to bodge together from ICs you could buy off-the-shelf.

Power sequencing, power management, data acquisition (like keypad-scanners), frequency detection, phase-locked loops, PWM controller, stuff like that.

For real number-crunching and DSP-tasks that aren't appropriate to a general-purpose CPU a FPGA is what you would go with.

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support from native speakers who also understand the product. Let's face i t, often the problem with docs is not really the language they were origina lly written in, it's how well the writer can write. I know my tech writing is not as good as a good writer would do. I think it takes some training to make a writer understand methods and goals. Not entirely unlike teachin g. Not many are natural teachers.

eeded to realize it just wasn't a good fit to this design. The design uses a current regulator that is only a diode, a cap, two transistors and a few resistors. Works well to charge a supercap. A pair of comparators and so me logic to provide a mute function for the sounder. I decided I didn't wa nt to just turn on a sounder, so added a chip to provide pulsing, four shor ts and a pause repeated every N seconds.

ut adding logic. It really needs three states, so two FF and some gates, b ut eventually I found a way to do it with the one FF and inverters with an RC to delay the clock from the release of the reset.

ators, logic (enough to do it "right") and even a pass transistor. But the PFET seems to be on or off. I didn't see any way to control it and no op- amps, so I guess that's not the intent. It would have still required a dio de to prevent the supercap from powering the power rail when down. I looke d at the chips with regulators w/ current limits, but just didn't work well . I also was not sure it would work at all in this job since it would need to be powered by both sources depending on which was up and which was down . Close, but no cigar.

ent limiter. That would be 4 ICs and seven or so passives replaced. Not s ure it's worth it. Part of the requirements is to be able to locally sourc e all components. I'm not sure that is possible for electronics just anywh ere. I've tried to use parts that are available from both Mouser and Digik ey and more than one manufacturer. I think the Greenpak stuff is just not very universal yet.

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y time you need something more I'm your man with FPGAs. Lattice has a wide selection of smaller parts in smaller packages, some non-BGA. I don't kno w Verilog well, but VHDL is not hard. People complain about the strong typ ing, but they are wussies and expect tools to read their minds. Then when the tool makes a mistake, the blame it on the tool! With VHDL the tool won 't think for you. You have to tell it what you want. Mostly that means us ing a data type that suits your needs. Not hard, but it takes a couple of days to get the hang of it. I'm happy to help you want to make the plunge.

That's what everyone thinks. I find FPGA programming to be more natural wi th fewer restrictions. I think most of us have a natural bias from having learned sequential programming early on so we accept the limitations and ad apt to it easily. When programming tasks get a bit complicated it can be a PITA to manage real time events without a lot of thought and effort.

The issues of designing in an FPGA are strictly from the problem, not from the solution really. In essence everything in hardware runs in parallel un less you work hard to implement sequential processing, which is required so metimes. A coworker impressed me once with a design three of us were worki ng on. It had a bunch of faster logic running at 77 MHz, but also had to d o some significant processing of the blocks of data (measuring statistics o f data flows and error rates).

He put together what was essentially a very targeted processor, sequenced r ather than being instruction based. Still it pulled in data from the buffe r and performed basic arithmetic and compiled the statistics. The sequenti al approach was required because we were retrofitting advanced features in an existing product with a 10k LUT FPGA, IIRC. So being size limited we di d what we had to.

Totally different from trying to shoehorn more into a CPU. With a CPU you need to map out things that are hard to measure and make the timings all fi t on a single processor. Talk about a headache! This is typically solved in CPUs by using a process that is way faster than required and with a lot more memory than required costing more dollars. But we are used to it, so we don't find it a bother.