An ideal pulse-width limiter has zero rising-edge delay, programmable width, and zero recovery time. This isn't too bad:
The first gate is acting like a line receiver, so doesn't count against my prop delay; so delay = 1 ns.
Recovery time should be pretty good, under 10 ns maybe. If I tease the exponential a bit, I could reduce the cap and improve recovery.
Hmm, two gate delays? I guess you're discounting the first one, fair enough.
Could use a diode gate, or a series resistor and a somewhat beefier transistor, to shunt the input after the delay.
To do any less than what you've shown, you've got to incur some sort of quirkiness, such as sensitivity to load, which the above strategy will have. (Hopefully, the diode gate or resistor feeds a minimal load, like a single logic pin and no trace length.) The sensitivity could be further worsened\\\\optimized by adding a peaking coil or two...
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:
OK, does the circle on the fet input mean an inverter? So the fet is normally on, closed, then open when the pulse comes?
George H.
A series L in the discharge path would help, make the discharge critically damped instead of exponential. I'll probably have 30 or 40 ns minimum low time, so may not benefit from an L just now.
That NC7 analog switch (actually sold as a bus switch) is active-low-on. It's a dual, so I may as well use both sections in parallel to discharge my cap.
Oh, the part number is typo'd. It should be NC7WB3306.
Feed an open transmission line for fixed time period, trombone assembly for adjustable..
If I use both switch sections in parallel, that's below 2 ohms discharge resistance. The critical inductor value would be a couple of nH, and I probably have that just in wirebonds and strays. It will probably ring on the discharge with no added L.
Not in roughly 1/4 of a square inch.
And something would have to discharge that line, no?
PW_Lim_1.JPG
You haven't really explained anything about your application. It seems like you're making (almost) a low-prop-time programmable one-shot. Are there any of those that might work?
-F
It's not a one-shot, it's a pulse width limiter. I'm ultimately going to drive a transmission-line transformer, and I don't want the user's input pulses to be allowed to be wide enough to saturate the core.
Narrow pulses pass right through with 2 ns delay. Longer pulses get truncated to a programmable width.
This is part of an interlock to protect your T-line xfrmr. Don't call it a pulse width limiter.
If you ever designed anything, you could call it whatever you please.
Ah, Thanks I had the same question.
I wish more people would post circuit questions.
I've been thinking about measuring heat capacity. Maybe a FET to give a heat pulse and then measure temperature change. (with the body diode) Sample attached to the fet and some thermally 'driven shield' around the sample space. A pulse and response system.
George H.
Drive it with a CCS, or current limiting resistor.
Let the user saturate it, it's their signal to screw up. Ferrite doesn't burn. ;-)
Tim
Oh, the supply will be current limited, voltage and current limit programmable by more DACs. But I don't want ugly pulses.
I suppose that most people have, or think they have, personal or business reasons why they can't show their work. Or don't design circuits at all.
I've pulsed one transistor of a dual, and used the other to measure temperature vs time. That's sort of fun. The temperature measurement is continuous, not time-shared with the heating pulse.
Yeah, or they don't want to appear like an idiot. (which never stops me.)
Right a dual might be better. I think I saw Fets that had a built in diode for temperature sensing. I should look at those.
George H.
I have seen this phenomenon with several times with communications protocols.
Some companies demand NDAs to get access to their protocol specifications.While in some cases, this might be a commercial interest of keeping competitors out of their product family, but in many cases, their protocol specification is so dumb that detecting bad specification only takes 5 minutes.
It is understandable that the companies try to hide such embarrassing protocol specifications or device designs :-)
They probably think it's great.
That's good if you want to probe a noisy system, because you can send a large number of pulses in, and sum all the noisy responses in memory. There's a lovely system called a 'hammer seismometer' that uses some percussor (anything from a sledge hammer up to a one-piston internal combustion gizmo) and a triggered receiver. Signal averaging and patience go in, rewarding data comes out.
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