Hi,
Im working on a final project for a digital design course and I have a question regarding how to find the sizes of different logical gates in order to minimize the delay across the circuit (effectively the critical path). I have a picture of the path if i get your email, if not here is a sketch of it.
cin (2*cunit) -> 2 input OR -> 2 input AND -> 2 input OR -> 2 input AND -> 2 input OR -> 2 input AND -> 2 input OR -> 2 input XOR -> 16 cunit
cunit is a parameter we use in class. cunit = capacitance of an inverter.
This is the path and the question is how to size all this stuff such that the delay is minimized. Any help would be appreciated as the project is due Wednesday night!
Thank you.
Paul